SAA5700 查看數據表（PDF） - Philips Electronics
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SAA5700 Datasheet PDF : 24 Pages
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Philips Semiconductors
Chinese Character System Teletext
(CCST) decoder
Preliminary specification
SAA5700
SYMBOL PIN
I/O
DESCRIPTION
RA4
32
O bit 4 of address to DRAM, ROM and IC
VSS1
n.c.
33
ground 0 V power supply digital; connected internally to VSS2 and VSS3
34
−
not connected
VDDD1
RA5
35
supply +5 V power supply digital; connected internally to VDD2
36
O bit 5 of address to DRAM, ROM and IC
RA6
37
O bit 6 of address to DRAM, ROM and IC
RA7
38
O bit 7 of address to DRAM, ROM and IC
n.c.
39
−
not connected
RA8
40
O bit 8 of address to DRAM, ROM and IC
RA9
41
O bit 9 of address to DRAM, ROM and IC
RAS
n.c.
42
O row address strobe to DRAM; active LOW
43
−
not connected
WE
44
O write enable to DRAM and IC; active LOW
i.c.
RD0
45
−
internally connected; do not use
46
I/O bit 0 of data bus to/from DRAM, ROM and IC
RD1
47
I/O bit 1 of data bus to/from DRAM, ROM and IC
VDDD2
VSS2
n.c.
48
supply +5 V power supply digital; connected internally to VDD1
49
ground 0 V power supply digital; connected internally to VSS1 and VSS3
50
−
not connected
RD2
51
I/O bit 2 of data bus to/from DRAM, ROM and IC
RD3
52
I/O bit 3 of data bus to/from DRAM, ROM and IC
CAS
53
O column address strobe to DRAM; active LOW
RA10
54
O bit 10 of address to DRAM, ROM and IC
RD7
55
I/O bit 7 of data bus to/from DRAM, ROM and IC
RD6
56
I/O bit 6 of data bus to/from DRAM, ROM and IC
RD5
57
I/O bit 5 of data bus to/from DRAM, ROM and IC
RD4
58
I/O bit 4 of data bus to/from DRAM, ROM and IC
RESET
59
I
chip/processor reset input (active HIGH)
DDA
SCL
SDA
60
I/O bidirectional serial data to/from optional Decryptor
61
I
primary I2C-bus serial clock input
62
I/O primary I2C-bus serial data
DCL
63
O serial clock to optional Decryptor
OSCIN
64
I
oscillator input from crystal/external clock input
1997 May 16
5
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