Philips Semiconductors
YUV-to-RGB Digital-to-Analog
Converter (DAC)
Preliminary specification
SAA7167
AC CHARACTERISTICS
Tamb = 0 to 70 °C.
SYMBOL
PARAMETER
MIN.
fclk
δ
PCLK
tsu1
th1
tsu2
th2
tsu3
th3
tsw
Tgroup
tr
tf
ts
tPD
video clock rate
−
duty factor of VCLK
−
pixel clock rate (8-bit pixel colour key); see Fig.4
−
pixel clock rate (2 × 8-bit pixel colour key; mode 1); −
see Fig.5
pixel clock rate (2 × 8-bit pixel colour key; mode 2); −
see Fig.6
pixel clock rate (3 × 8-bit pixel colour key); see Fig.7 −
duty factor of PCLK
40
digital input set-up time to VCLK rising edge
3
digital input hold time to VCLK rising edge
3
digital input set-up time to PCLK rising edge
3
digital input hold time to PCLK rising edge
3
digital input set-up time to PCLK falling edge
3
digital input hold time to PCLK falling edge
3
switching time between video DAC/analog inputs;
−
note 1
overall group delay from digital video inputs to analog
outputs (see Fig.8):
YUV video input mode
−
RGB video input mode
−
DAC analog output rise time (see Fig.8); note 2
−
DAC analog output fall time (see Fig.8); note 2
−
DAC analog output settling time (see Fig.8); note 3 −
DAC analog output propagation delay (see Fig.8);
−
note 4
Analog outputs from analog inputs
Gv
voltage gain
−
B
bandwidth (−3 dB)
−
SR
slew rate
−
TYP.
−
50
−
−
−
−
50
−
−
−
−
−
−
−
MAX.
50
−
50
40
80
75
60
−
−
−
−
−
−
15
20TVCLK + tPD −
12TVCLK + tPD −
5
−
5
−
−
15
15
−
2.0
−
75
−
90
−
UNIT
MHz
%
MHz
MHz
MHz
MHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
V/µs
Notes
1. Switching time measured from the 50% point of the EXTKEY transition edge to the 50% point of the selected analog
output transition.
2. DAC output rise/fall time measured between the 10% and 90% points of full scale transition.
3. DAC settling time measured from the 50% point of full-scale transition to the output remaining within ±1 LSB.
4. DAC analog output propagation delay measured from the 50% point of the rising edge of VCLK to the 50% point of
full-scale transition.
1995 Nov 03
10