SAA7392 查看數據表（PDF） - Philips Electronics
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SAA7392 Datasheet PDF : 76 Pages
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Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
7.3.1 CLOCK PRESET REGISTER (CLOCKPRE)
Table 17 Clock Preset Register (address 12H) - WRITE
7
CL1Div
6
GateBClk
5
Div.1
4
Div.0
3
Mux2
2
Div2.2
1
Div2.1
0
Div2.0
Table 18 Description of ClockPre bits
BIT
SYMBOL
DESCRIPTION
7
CL1Div If CL1Div = 0, then CL1 output frequency is 1⁄3fclk. If CL1Div = 1, then CL1 output
frequency is 1⁄2fclk.
6
GateBClk If GateBClk = 0, then I2S output bit clock gating is disabled. If GateBClk = 1, then I2S
output bit clock gating enabled, BCLK is output, clock is automatically stopped if FIFO
underflows (this is known as Flow control mode).
5
Div.1
These 2 bits select the system clock frequency (fclk); see Table 19. This frequency
4
Div.0
should be programmed for the expected disc channel rate (e.g. 4.33 MHz for 1 × CD)
within the following constraints:
C-----h---a----n---n-2--e----l---r--a---t--e- < fclk < 4 × Channel rate
3
2 to 0
Mux2
Div2<2:0>
In this clock range, reliable bit detection is possible. All data found will be written to the
FIFO. It is the responsibility of the user to select system clock values so that the FIFO
performance is controlled.
If Mux2 = 0, then N (bit clock divider pre-scaler) = 1. If Mux2 = 1, then N = M.
These 3 bits select the BCLK frequency (fBCLK); see Table 20. It is the responsibility of
the user to select BCLK values so that the FIFO performance is controlled.
Table 19 Selection of system clock frequency
Div.1
0
0
1
1
Div.0
0
1
0
1
M × fXTLI
0.5 × M × fXTLI
0.25 × M × fXTLI
0.125 × M × fXTLI
SYSTEM CLOCK FREQUENCY (fclk)
Table 20 Selection of BCLK frequency
Div2.1
0
0
0
0
1
1
1
1
Div2.1
0
0
1
1
0
0
1
1
Div2.0
0
1
0
1
0
1
0
1
N × fXTLI
N × fXTLI
1/2(N × fXTLI)
1/3(N × fXTLI)
1/4(N × fXTLI)
1/6(N × fXTLI)
1/8(N × fXTLI)
1/12(N × fXTLI)
BCLK FREQUENCY (fBCLK)
2000 Mar 21
17
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