Q67120-C0581 查看數據表（PDF） - Siemens AG

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Q67120-C0581

8-Bit CMOS Single-Chip Microcontroller Family

Siemens AG 

Memory Organization

3.4 Architecture of the XRAM

The contents of the XRAM is not affected by a reset or HW Power Down. After power-up the

contents is undefined, while it remains unchanged during and after a reset or HW Power Down if the

power supply is not turned off.

The additional On-Chip RAM is logically located in the "external data memory" range at the upper

end of the 64 KByte address range (F800H -FBFFH). Nevertheless when XRAM is enabled the

address range F800H to FFFFH is occupied. This is done to assure software compatibility to SAB

80C517A. It is possible to enable and disable (only by reset) the XRAM. If it is disabled the device

shows the same behaviour as the parts without XRAM, i.e. all MOVX accesses use the external bus

to physically external data memory.

3.4.1 Accesses to XRAM

Because the XRAM is used in the same way as external data memory the same instruction types

must be used for accessing the XRAM.

Note:

If a reset occurs during a write operation to XRAM, the effect on XRAM depends on the cycle which

the reset is detected at (MOVX is a 2-cycle instruction):

Reset detection at cycle 1: The new value will not be written to XRAM. The old value is not

affected.

Reset detection at cycle 2: The old value in XRAM is overwritten by the new value.

Accesses to XRAM using the DPTR

There are a Read and a Write instruction from and to XRAM which use one of the 16-bit DPTR for

indirect addressing. The instructions are:

MOVX A, @DPTR

(Read)

MOVX @DPTR, A

(Write)

Normally the use of these instructions would use a physically external memory. However, in the

SAB 80C515A the XRAM is accessed if it is enabled and if the DPTR points to the XRAM address

space (DPTR ≥ F800H).

Semiconductor Group

3-8

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