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Q67101-H6789 查看數據表(PDF) - Siemens AG

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Q67101-H6789 Datasheet PDF : 272 Pages
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SAB 82532/SAF 82532
Introduction
• Support of bus configuration by collision detection and resolution
• Statistical multiplexing
• Continuous transmission of 1 to 32 bytes possible
• Programmable preamble (8 bit) with selectable
repetition rate (HDLC/SDLC and BISYNC)
• Data rate up to 10 Mbit/s
• Master clock mode with data rate up to 4 Mbit/s
Protocol Support (HDLC/SDLC)
• Various types of protocol support depending on operating mode
– Auto mode (automatic handling of S- and I-frames)
– Non-auto mode
– Transparent mode
• Handling of bit oriented functions
• Support of LAPB/LAPD/SDLC/HDLC protocol in auto mode
(I- and S-frame handling)
• Modulo-8 or modulo-128 operation
• Programmable time-out and retry conditions
• Programmable maximum packet size checking
MP Interface and Ports
• 64 byte FIFOs per channel and direction (byte or word access)
• 8/16 bit microprocessor bus interface (Intel or Motorola type)
• All registers directly accessible (byte and word access)
• Efficient transfer of data blocks from/to system memory via DMA or interrupt request
• Support of Daisy Chaining and Slave Operation with Interrupt Vector generation
• 8-bit programmable bi-directional universal port
General
• Advanced CMOS technology
• Low power consumption: active 40 mW at 2 MHz/standby 5 mW (typical values)
• P-LCC-68 Package
• P-MQFP-80 Package
Semiconductor Group
8
07.96

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