SAM4S 查看數據表（PDF） - Atmel Corporation

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SAM4S

AT91SAM ARM-based Flash MCU

Atmel Corporation 

7.5 Master to Slave Access

All the Masters can normally access all the Slaves. However, some paths do not make sense,

for example allowing access from the Cortex-M4 S Bus to the Internal ROM. Thus, these paths

are forbidden or simply not wired, and shown as “-” in the following table.

Table 7-3. SAM4S Master to Slave Access

Slaves

0

1

2

3

4

Masters

0

1

2

3

Cortex-M4 I/D

Bus

Cortex-M4 S

Bus

PDC

CRCCU

Internal SRAM

-

X

X

X

Internal ROM

X

-

X

X

Internal Flash

X

-

-

X

External Bus Interface

-

X

X

X

Peripheral Bridge

-

X

X

-

7.6 Peripheral DMA Controller

• Handles data transfer between peripherals and memories

• Low bus arbitration overhead

– One Master Clock cycle needed for a transfer from memory to peripheral

– Two Master Clock cycles needed for a transfer from peripheral to memory

• Next Pointer management for reducing interrupt latency requirement

The Peripheral DMA Controller handles transfer requests from the channel according to the fol-

lowing priorities (Low to High priorities):

Table 7-4. Peripheral DMA Controller

Instance name

Channel T/R

PWM

Transmit

TWI1

Transmit

TWI0

Transmit

UART1

Transmit

UART0

Transmit

USART1

Transmit

USART0

Transmit

DACC

Transmit

SPI

Transmit

SSC

Transmit

HSMCI

Transmit

30 SAM4S Series [Preliminary]

11100BS–ATARM–31-Jul-12

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