SC1112(2001) 查看數據表（PDF） - Semtech Corporation
零件编号
产品描述 (功能)
生产厂家
SC1112 Datasheet PDF : 21 Pages
| |||
SC1112
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: 5VSTBY=4.75V to 5.25V; VTTIN=3.3V; TA = 25°C
Parameter
Symbol
Conditions
Min
Typ
Max Units
Linear Sections (Cont.)
Output Voltage VTT
Output Voltage AGP
Output Voltage ADJ
VTTSEN Bias Current
(SC1112)
(SC1112A)
VTT1.2
IO = 0 to 2A, VTTSEL = LOW
1.176
1.200
1.224 V
(SC1112)
VTT1.25
IO = 0 to 2A, VTTSEL = LOW 1.225
1.250
1.275
VTT1.5
IO = 0 to 2A, VTTSEL = HIGH 1.470
1.500
1.530 V
AGP
1.5
I = 0 to 2A, AGPSEL = LOW 1.470
O
1.500
1.530 V
AGP3.3
IO = 0 to 2A, AGPSEL = HIGH 3.234
3.300
V
ADJ
IO = 0 to 2A
-2% 1.2*(1+RA/RB) +2% V
IbiasVTTSEN
90
120
140 µA
VTTSEN Bias Current
(SC1112A)
IbiasVTTSEN
1
5
µA
AGPSEN Bias Current
IbiasAGPSEN
110
150
170 µA
ADJSEN Bias Current
IbiasADJSEN
1
5
µA
VTT Gate Current
IsourceVTTgate 5VSTBY = 4.75V, Vgate = 3.0V
500
µA
IsinkVTTgate
500
µA
AGP Gate Current
IsourceAGPgate 5VSTBY = 4.75V, Vgate = 3.0V
500
µA
IsinkAGPgate
500
µA
ADJ Gate Current
IsourceADJgate 5VSTBY = 4.75V, Vgate = 3.0V
500
µA
IsinkADJgate
500
µA
Load Regulation
LOADREG
VTTIN = 3.30V, IO = 0 to 2A
0.3
%
Line Regulation
LINEREG
VTTIN = 3.13V to 3.47V,
Io = 2A
0.3
%
Gain (AOL)(2)
GAINLDO
LDOS Output to GATE
50
dB
Notes:
(1) All electrical characteristics are for the application circuit on page 19.
(2) Guaranteed by design
(3) Tracking Difference is defined as the delta between 3.3V Vin and the VTT, AGP, ADJ output voltages during the linear ramp up until
regulation is achieved. The Tracking Voltage difference might vary depending on MOSFETs Rdson, and Load Conditions.
(4) During power up, an internal short circuit glitch timer will start once the VTT Input Voltage exceeds the VTTINTH (1.5V). During the glitch
timer immunity time, determined by the Delay capacitor (Delay time is approximately equal to (Cdelay*SCTH)/ISC), the short circuit
protection is disabled to allow VTT output to rise above the trip threshold (0.7V). If the VTT output has not risen above the trip
threshold after the immunity time has elapsed, the VTT output is latched off and will only be enabled again if either the VTT input
voltage or the 5VSTBY is cycled.
(5) PWRGD pin is kept low during the power up, until the VTT output has reached its PG or PG level. At that time the PWRGD
td1.2
td1.5
source current IPG (20uA) is enabled and will start charging the external PWRGD delay capacitor connected to the DELAY pin. Once the
capacitor is charged above the PG
(1.5V), the PWRGD pin is released from ground.
Delay_TH
2001 Semtech Corp.
3
www.semtech.com
Share Link: 