POWER MANAGEMENT
Block Diagram
SC1182 & SC1183
CS- CS+
VCC
EN
VID4
VID3
VID2
VID1
VID0
VOSENSE
PWRGOOD
OVP
LDOS1
GATE1
REF
70mV
+
-
CURRENT LIMIT
D/A
R
OSCILLATOR
Q
S
+
-
OPEN
COLLECTORS
+
-
VCC
+
-
FET
CONTROLLER
2.5V/ADJ.
-
+
+
-
ERROR
AMP
AGND
1.265V
REF
FET
CONTROLLER
1.5V/ADJ.
LEVEL SHIFT
AND HIGH SIDE
DRIVE
SHOOT
THRU
CONTROL
BSTH
DH
PGNDH
SYNCHRONOUS
DRIVE
BSTL
DL
PGNDL
AGND
LDOV
GATE2 LDOS2 AGND
Setting LDO Output Voltage.
For the SC1183, LDO Output voltages must be set by se-
lecting appropriate resistor values. These values may be
determined from the eqution below, or from the table at
right.
VOUT
=
1.265 ⋅ (RA
RB
+ RB ) + (IFB
⋅RA)
where :
IFB = Feedback pin bias current
RA = Top feedback resistor
RB = Bottom feedback resistor
See layout diagram for clarification
RA must be low enough so that the (IFB ⋅ RA ) term
does not cause significant error
VOUT LDO1 (LDO2)
3.45V
3.30V
3.10V
2.90V
2.80V
2.50V
1.50V
© 2001 Semtech Corp.
5
RB
RA
105Ω
105Ω
102Ω
100Ω
100Ω
100Ω
100Ω
182Ω
169Ω
147Ω
130Ω
121Ω
97.6Ω
18.7Ω
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