SC4611 查看數據表（PDF） - Semtech Corporation
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SC4611 Datasheet PDF : 11 Pages
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SC4611
POWER MANAGEMENT
Applications Information (Cont.)
The classical Type III compensation network can be built
around the error amplifier as shown below
C3
The design guidelines are as following:
1. Set the loop gain crossover frequency wC for given
switching frequency.
C2 R3
R2
C1
R1
-
+
Vref
2. Place an integrator in the origin to increase DC and low
frequency gains.
3. Select wZ1 and wZ2 such that they are placed near wO to
dampen peaking; the loop gain has –20 dB rate to go
across the 0 dB line for obtaining a wide bandwidth.
Figure 1. Voltage Mode Buck Converter Compensation
Network
The transfer function of the compensation network is as
follows:
(1 + s )(1 + s )
GCOMP (s)
=
ωI
s
⋅
(1 +
ωZ1
s )(1 +
ωZ 2
s)
ωP1
ωP2
where,
ωZ1
=
1
R2C1
,
ωZ 2
=
(R1
1
+ R3)C2
ωI
=
1
R1(C1 +
C3)
,
ωP1
=
1
R3C2
,
1
ωP2
=
R2
C1C3
C1 +C3
T
ω Z1
ωo
Loop gain T(s)
ωZ2
Gd
ωc
0dB
ω p1
ω p2
4. Cancel wESR with compensation pole wP1 (wP1 = wESR ).
5. Place a high frequency compensation pole wP2 at half
the switching frequency to get the maximum attenuation
of the switching ripple and the high frequency noise with
the adequate phase lag at wC.
PCB LAYOUT FOR SC4611
Careful attention to layout requirements is necessary for
successful implementation of the SC4611 PWM controller.
High switching currents with fast rise and fall times are
present in the application and their effect on ground plane
voltage differentials must be understood and minimized.
A good layout with minimum parasitic loop areas will
a) reduce EMI
b) lower ground injection currents, resulting in electrically
“cleaner” grounds for the rest of the system and
c) minimize source ringing, resulting in more reliable gate
switching signals.
LAYOUT GUIDELINES
In the following QT and QB denote the high side and low
side MOSFETs respectively.
ω ESR
Figure 2. Simplified asymptotic diagram of buck power
stage and its compensated loop gain.
1) A ground plane should be used. The number and position
of ground plane interruptions should be minimised so as
not to compromise ground plane integrity. Isolated or semi-
isolated areas of the ground plane may be deliberately
introduced to constrain ground currents into particular
paths, such as the output capacitor or the QB source.
2004 Semtech Corp.
9
www.semtech.com
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