SC4519H 查看數據表（PDF） - Semtech Corporation
零件编号
产品描述 (功能)
生产厂家
SC4519H Datasheet PDF : 14 Pages
| |||
SC4519H
POWER MANAGEMENT
Application Information (Cont.)
The junction temperature of the SC4519H can be
further determined by:
TJ = TA + θJA ⋅ Ptotal
θ JA is the thermal resistance from junction to ambient.
Its value is a function of the IC package, the application
layout and the air cooling system.
2 IN
5 EN
8 SYNC
SC4519H
SW 3
FB 6
COMP 7
C5
L1
R1
C
Vout
C4
R2
R3
D2
The freewheeling diode also contributes a significant
portion of the total converter loss. This loss should be
minimized to increase the converter efficiency by using
Schottky diodes with low forward drop (V ).
F
Pdiode = VF ⋅Io ⋅ (1− D)
Figure 3. Compensation network provides 2 poles and
1 zero.
Loop Compensation Design
The compensation network gives the following
characteristics:
The SC4519H has an internal error amplifier and requires
a compensation network to connect between the COMP
pin and GND pin as shown in Figure 3. The compensation
network includes C4, C5 and R3. R1 and R2 are used to
program the output voltage according to:
VO
=
0.8 • (1+
R1
R2
)
Assuming the power stage ESR (equivalent series
resistance) zero is an order of magnitude higher than
the closed loop bandwidth, which is typically one tenth of
the switching frequency, the power stage control to output
transfer function with the current loop closed (Ridley
model) for the SC4519H will be as follows:
Where:
G COMP (s)
=
ω1
⋅
s
⋅
1+
s
ωZ
(1 +
s
ωP2
)
⋅
gm
⋅
R2
R1 + R 2
ω1
=
C4
1
+
C5
ωZ
=
1
R3 ⋅ C4
ωP2
=
C4 + C5
R3 ⋅ C4 ⋅ C5
G VD
(s)
=
5
1+
⋅
RL
s
1
RL ⋅ C
Where:
RL – Load and
C – Output capacitor.
The goal of the compensation design is to shape the loop
to have a high DC gain, high bandwidth, enough phase
margin, and high attenuation for high frequency noises.
Figure 3 gives a typical compensation network which
offers 2 poles and 1 zero to the power stage:
The loop gain will be given by:
T(s)
=
GCOMP (s) ⋅ GVD (s)
=
4.25
⋅ 10 −3
⋅
RL
C4
⋅
R2
R1 + R2
⋅
1
s
(1+
1+
s
ωZ
s
ωP1
)
⋅
(1
+
s
ωP2
)
Where:
ωp1
=
1
RL ⋅C
One integrator is added at origin to increase the DC gain.
ωZ is used to cancel the power stage pole ωP1 so that the
loop gain has –20dB/dec rate when it reaches 0dB line.
ωP2 is placed at half switching frequency to reject high
frequency switching noises. Figure 4 gives the asymptotic
diagrams of the power stage with current loop closed
and its loop gain.
2007 Semtech Corp.
10
www.semtech.com
Share Link: 