SCN2681 查看數據表（PDF） - Philips Electronics
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SCN2681 Datasheet PDF : 30 Pages
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Philips Semiconductors
Dual asynchronous receiver/transmitter (DUART)
Product specification
SCN2681
BLOCK DIAGRAM
8
D0–D7
BUS BUFFER
RDN
WRN
CEN
4
A0–A3
RESET
OPERATION CONTROL
ADDRESS
DECODE
R/W CONTROL
INTRN
INTERRUPT CONTROL
IMR
ISR
CHANNEL A
TRANSMIT
HOLDING REG
TRANSMIT
SHIFT REGISTER
RECEIVE
HOLDING REG (3)
RECEIVE
SHIFT REGISTER
MRA1, 2
CRA
SRA
CHANNEL B
(AS ABOVE)
TxDA
RxDA
TxDB
RxDB
X1/CLK
X2
TIMING
BAUD RATE
GENERATOR
CLOCK
SELECTORS
COUNTER/
TIMER
XTAL OSC
CSRA
CSRB
ACR
CTUR
CTLR
INPUT PORT
CHANGE OF
STATE
DETECTORS (4)
IPCR
ACR
7
IP0-IP6
OUTPUT PORT
FUNCTION
SELECT LOGIC
OPCR
OPR
8
OP0-OP7
VCC
GND
SD00085
Figure 2. Block Diagram
BLOCK DIAGRAM
The SCN2681 DUART consists of the following eight major sections:
data bus buffer, operation control, interrupt control, timing,
communications Channels A and B, input port and output port.
Refer to the block diagram.
Data Bus Buffer
The data bus buffer provides the interface between the external and
internal data buses. It is controlled by the operation control block to
allow read and write operations to take place between the controlling
CPU and the DUART.
Operation Control
The operation control logic receives operation commands from the
CPU and generates appropriate signals to internal sections to
control device operation. It contains address decoding and read and
write circuits to permit communications with the microprocessor via
the data bus buffer.
Interrupt Control
A single active-Low interrupt output (INTRN) is provided which is
activated upon the occurrence of any of eight internal events.
Associated with the interrupt system are the Interrupt Mask Register
1998 Sep 04
7
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