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MRFIC0917 查看數據表(PDF) - Motorola => Freescale

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MRFIC0917 Datasheet PDF : 10 Pages
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APPLICATIONS INFORMATION
Design Philosophy
The MRFIC0917 is a two–stage Integrated Power Amplifier
designed for use in cellular phones, especially for those used
in GSM Class IV, 3.6 V operation. Due to the fact that the in-
put, output and some of the interstage matching is accom-
plished off chip, the device can be tuned to operate anywhere
within the 800 to 1000 MHz frequency range.
This capability makes the MRFIC0917 suitable for portable
cellular applications such as:
S
3.6 V 900 MHz DAMPS
S
3.6 V 900 MHz PDC
RF Circuit Considerations
The MRFIC0917 can be tuned by changing the values and/
or positions of the appropriate external components. Refer to
Figure 2, a typical GSM Class IV applications circuit.
The input match is a shunt–C, series–L, low–pass structure
and can be retuned as desired with the only limitation being the
on–chip 12 pF blocking capacitor. For saturated applications
such as GSM and analog cellular, the input match should be
optimized at the rated RF input power.
Interstage matching can be optimized by changing the value
and/or position of the decoupling capacitor on the VD1 supply
line. Moving the capacitor closer to the device or reducing the
value increases the frequency of resonance with the induc-
tance of the device’s wirebonds and leadframe pin.
Output matching is accomplished with a two–stage low–pass
network as a compromise between bandwidth and harmonic
rejection. Implementation is through chip capacitors mounted
along a 30 or 50microstrip transmission line. Values and
positions are chosen to present a 2loadline to the device
while conjugating the device output parasitics. The network
must also properly terminate the second and third harmonics to
optimize efficiency and reduce harmonic output. When low–Q
commercial chip capacitors are used for the shunt capacitors,
loss can be reduced by mounting two capacitors in parallel to
achieve the total value needed.
Loss in circuit traces must also be considered. The output
transmission line and the bias supply lines should be at least
0.6 mm in width to accommodate the peak circulating currents
which can be as high as 2 amperes. The bias supply line which
supplies the output should include an RF choke of at least 8
nH, surface mount solenoid inductors or equivalent length of
microstrip lines. Discrete inductors will usually give better effi-
ciency and conserve board space.
The DC blocking capacitor required at the output of the de-
vice is best mounted at the 50impedance point in the circuit
where the RF current is at a minimum and the capacitor loss
will have less effect.
Power Control Using the MC33169
The MC33169 is a dedicated GaAs power amplifier support
IC which provides the –4 V required for VSS, an N–MOS drain
switch interface and driver and power supply sequencing. The
MC33169 can be used for power control in applications where
the amplifier is operated in saturation since the output power
in non–linear operation is proportional to VD2. This provides a
very linear and repeatable power control transfer function.
This technique can be used open–loop to achieve 20–25 dB
dynamic range over process and temperature variation. With
careful design and selection of calibration points, this tech-
nique can be used for GSM phase II control where 29 dB dy-
namic range is required, eliminating the need for the
complexity and cost of closed–loop control.
The transmit waveform ramping function required for sys-
tems such as GSM can be implemented with a simple Sallen
and Key filter on the MC33169 control loop. The amplifier is
then ramped on as the VRAMP pin is taken from 0 V to 3 V. To
implement the different power steps required for GSM, the
VRAMP pin is ramped between 0 V and the appropriate voltage
between 0 V and 3 V for the desired output power.
For closed–loop configurations using the MC33169,
MMSF4N01HD N–MOS switch and the MRFIC0917 provide a
typical 1 MHz 3 dB loop bandwidth. The STANDBY pin must
be enabled (3 V) at least 800 µs before the VRAMP pin goes
high and disabled (0 V) at least 20 µs before the VRAMP pin
goes low. This STANDBY function allows for the enabling of
the MC33169 one burst before the active burst thus reducing
power consumption.
Biasing Considerations
Gate bias is supplied to each stage separately through resis-
tive division of the VSS voltage. The top of each divider is brought
out through pins 12 and 13 (VG2 and VG1 respectively) allowing
gate biasing through use of external resistors or positive volt-
ages. This allows setting the quiescent current of each stage
separately.
For applications where the amplifier is operated close to
saturation, such as GSM and analog cellular, the gate bias
can be set with resistors. Variations in process and tempera-
ture will not affect amplifier performance significantly in these
applications. The values shown in the Figure 1 will set quies-
cent currents of 100 to 200 mA for the first stage and 600 to
1200 mA for the second stage.
For linear modes of operation, the quiescent current must
be more carefully controlled. For these applications, the VG
pins can be referenced to some tunable voltage which is set at
the time of radio manufacturing. Less than 1.0 mA is required
in the divider network so a DAC can be used as the voltage
source. Typical settings for 3.6 V linear operation are 150 mA
±5% for the first stage, and 750 mA ±5% for the second stage.
Conclusion
The MRFIC0917 offers the flexibility in matching circuitry and
gate biasing required for portable cellular applications. Together
with the MC33169 support IC, the device offers an efficient sys-
tem solution for TDMA applications such as GSM where satu-
rated amplifier operation is used.
Evaluation Boards
Evaluation boards are available for RF Monolithic Inte-
grated Circuits. For a complete list of currently available
boards and ones in development for newly introduced
product, please contact your local Motorola Distributor or
Sales Office.
MOTOROLA RF DEVICE DATA
MRFIC0917
9

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