MU9C1480A-70DC 查看數據表（PDF） - Music Semiconductors

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MU9C1480A-70DC

MU9C1480A/L LANCAMs®

Music Semiconductors 

MU9C1480A/L Draft

FUNCTIONAL DESCRIPTION Continued

or a forced compare), the Status register contains the

address of the Highest-Priority Matching location in that

device, concatenated with its page address, along with

flags indicating internal match, multiple match, and full.

When the Status register is read with a Command Read

cycle, the device with the Highest-Priority Match will

respond, outputting the System Match address to the DQ

bus. The internal Match (/MA) and Multiple Match (/MM)

flags are also output on pins. Another set of flags (/MF

and /FF) that are qualified by the match and full flags of

previous devices in the system also are available directly

on output pins, and are independently daisy-chained to

provide System Match and Full flags in vertically cascaded

LANCAM arrays. In such arrays, if no match occurs during

a comparison, read access to the memory and all the

registers except the Next Free register is denied to prevent

device contention. In a daisy chain, all devices will respond

to Command and Data Write cycles, depending on the

conditions shown in Tables 5a and 5b on page 12, unless

the operation involves the Highest-Priority Match address

or the Next Free address; in which case, only the specific

device having the Highest-Priority match or the Next Free

address will respond.

A Page Address register in each device simplifies vertical

expansion in systems using more than one LANCAM. This

register is loaded with a specific device address during

system initialization, which then serves as the higher-order

address bits. A Device Select register allows the user to

target a specific device within a vertically cascaded system

by setting it equal to the Page Address Register value, or

to address all the devices in a string at the same time by

setting the Device Select value to FFFFH.

Figure 1a shows expansion using a daisy chain. Note that

system flags are generated without the need for external

logic. The Page Address register allows each device in the

vertically cascaded chain to supply its own address in the

event of a match, eliminating the need for an external priority

encoder to calculate the complete Match address at the

expense of the ripple-through time to resolve the Highest-

Priority match. The Full flag daisy-chaining allows

Associative writes using a Move to Next Free Address

instruction, which does not need a supplied address.

Figure 1b shows an external PLD implementation of a simple

priority encoder that eliminates the daisy chain ripple-

through delays for systems requiring maximum performance

from many CAMs.

OPERATIONAL CHARACTERISTICS

Throughout the following, “aaaH” represents a three-digit

hexadecimal number “aaa,” while “bbB” represents a two-

digit binary number “bb.” All memory locations are written

to or read from in 16-bit segments. Segment 0 corresponds to

the lowest order bits (bits 15–0) and Segment 3 corresponds

to the highest order bits (bits 63–48).

THE CONTROL BUS

Refer to the Block Diagram on page 1 for the following

discussion. The inputs Chip Enable (/E), Write Enable (/W),

Command Enable (/CM), and Enable Daisy Chain (/EC) are

the primary control mechanism for the LANCAM. The /EC

input of the Control bus enables the /MF Match flag output

when LOW and controls the daisy chain operation.

Instructions are the secondary control mechanism. Logical

combinations of the Control Bus inputs, coupled with the

execution of Select Persistent Source (SPS), Select Persistent

Destination (SPD), and Temporary Command Override

(TCO) instructions allow the I/O operations to and from

the DQ15–0 lines to the internal resources, as shown in

Table 3 on page 9.

The Comparand register is the default source and

destination for Data Read and Write cycles. This default

state can be overridden independently by executing a Select

Persistent Source or Select Persistent Destination

instruction, selecting a different source or destination for

data. Subsequent Data Read or Data Write cycles will

access that source or destination until another SPS or SPD

instruction is executed. The currently selected persistent

source or destination can be read back through a TCO PS

or PD instruction. The sources and destinations available

for persistent access are those resources on the 64-bit bus:

Comparand register, Mask Register 1, Mask Register 2, and

the Memory array.

The default destination for Command Write cycles is the

Instruction decoder, while the default source for Command

Read cycles is the Status register.

Temporary Command Override (TCO) instructions provide

access to the Control register, the Page Address register,

the Segment Control register, the Address register, the Next

Free Address register, and Device Select register. TCO

Rev. 3.0 Draft

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