ADV7160KS170 查看數據表（PDF） - Analog Devices

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ADV7160KS170

96-Bit, 220 MHz True-Color Video RAM-DAC

Analog Devices 

ADV7160/ADV7162

TIMING CHARACTERISTICS (Cont.)1 (VAA2= +5 V; VREF = +1.235 V; RSET = 280 Ω. IOR, IOG, IOB (RL = 37.5 Ω, CL =10 pF).

All specifications TMIN to TMAX3 unless otherwise noted.)

JTAG PORT

Parameter

All Versions

Units

Conditions/Comments

PLL PERFORMANCE4

Jitter

250

PLL REFERENCE INPUT

PLLREF Frequency

900

40

VIH

2.0

VIL

0.8

PLLREF Period

25

1.67

PLLREF Duty Cycle

40

60

JTAG PERFORMANCE

TCK Frequency, t29

20

TCK High Time, t30

15

TCK Low Time, t31

15

TDI, TMS Setup Time, t32

15

TDI, TMS Hold Time, t33

15

Digital Input to TCK Setup Time, t34

15

Digital Input to TCK Hold Time, t35

15

TCLK to TDO Drive, t36

0

TCLK to TDO Valid, t37

20

TCLK to TDO Three-State, t38

5

15

ps rms

1σ

kHz min

MHz max

V max

V min

ns min

µs max

% min

% max

MHz max

ns min

ns min

ns max

ns max

ns max

ns max

ns min

ns min

ns min

ns max

NOTES

1TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.

2± 5% for all versions.

3Temperature range (TMIN to TMAX); 0°C to +70°C.

4Jitter is measured by triggering on the output clock, delayed by 15 µs and then measuring the time period from the trigger edge to the next edge of the output clock

after the delay. This measurement is repeated multiple times and the RMS value is determined.

Specifications subject to change without notice.

t32

TCK

t34

TMS, TDI

t29

t30

t31

t33

t35

DIGITAL

INPUT

TDO

t37

t36

TDO

t38

Figure 2. JTAG Timing

REV. 0

–5–

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