SI4126-F-GM 查看數據表（PDF） - Silicon Laboratories

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SI4126-F-GM

ISM RF SYNTHESIZER WITH INTEGRATED VCOS FOR WIRELESS COMMUNICATIONS

Silicon Laboratories 

Si4136/Si4126

Table 5. RF and IF Synthesizer Characteristics (Continued)

(VDD = 2.7 to 3.6 V, TA = –40 to 85 °C)

Parameter1

Symbol

Test Condition

Min

Typ

Max

Unit

RF1 Harmonic Suppression

Second Harmonic

—

–28

–20

dBc

RF2 Harmonic Suppression

—

–23 –20

dBc

IF Harmonic Suppression

—

–26 –20

dBc

RFOUT Power Level

RFOUT Power Level

IFOUT Power Level

RF1 Output Reference Spurs

ZL = 50RF1 active –7

ZL = 50RF2 active –7

ZL = 50 

–7

Offset = 1 MHz

—

–3.5 –0.5 dBm

–3.5 –0.5 dBm

–4

0

dBm

–63

—

dBc

Offset = 2 MHz

—

–68

—

dBc

Offset = 3 MHz

—

–70

—

dBc

RF2 Output Reference Spurs

Offset = 1 MHz

—

–63

—

dBc

Offset = 2 MHz

—

–68

—

dBc

Offset = 3 MHz

—

–70

—

dBc

Powerup Request to Synthesizer Ready3 tpup

Time

Powerup Request to Synthesizer Ready3 tpup

Time

Powerdown Request to Synthesizer Off4 tpdn

Time

Figures 4, 5

f> 500 kHz

Figures 4, 5

f 500 kHz

Figures 4, 5

—

80

100

s

—

40/f 50/f

—

—

100

ns

Notes:

1. f(RF) = 1 MHz, f(IF) = 1 MHz, RF1 = 2.4 GHz, RF2 = 2.1 GHz, IFOUT = 800 MHz, LPWR = 0, for all parameters

unless otherwise noted.

2. RF VCO tuning range limits are fixed by inductance of internally bonded wires.

3. From powerup request (PWDN or SEN during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF

synthesizers ready (settled to within 0.1 ppm frequency error).

4. From powerdown request (PWDN, or SENduring a write of 0 to bits PDIB and PDRB in Register 2) to supply current

equal to IPWDN.

Rev. 1.41

9

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