SI4702-C19 查看數據表（PDF） - Silicon Laboratories
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SI4702-C19 Datasheet PDF : 46 Pages
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Si4702/03-C19
Table 3. DC Characteristics1
(VD = VA = 2.7 to 3.6 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol Test Condition
Min
Typ
Max
Analog Operating Supply Current2
IA
Digital Operating Supply Current2
ID
ENABLE = 1
ENABLE = 1
—
10.8
—
—
3.3
—
Interface Operating Supply
Current2
IIO
ENABLE = 1
—
0.3
—
Total Operating Supply
Current2,3,4,5
IOP
ENABLE = 1
—
15.3
16.8
Low SNR signal
Total Operating Supply
Current2,3,4
Total Operating Supply
Current2,3,4,6
IOP
ENABLE = 1
IOP
ENABLE = 1
RDS = 1
—
14.4
15.9
—
14.9
16.4
Total Operating Supply
Current2,3,4,6
IOP
ENABLE = 1
RDS = 1,
—
15.8
16.8
Low SNR signal
Analog Powerdown Supply Current2,7
Digital Powerdown Supply Current2,7
IAPD
IDPD
ENABLE = 0
ENABLE = 0
—
3.5
—
—
2.5
—
Interface Powerdown Supply
Current2,7
IIOPD
ENABLE = 0
—
2.5
—
SCLK, RCLK inactive
Total Powerdown Supply Current2,7
IPD
ENABLE = 0
—
8.5
12.0
High Level Input Voltage8
VIH
0.7 x VIO
—
VIO + 0.3
Low Level Input Voltage8
VIL
–0.3
—
0.3 x VIO
High Level Input Current8
IIH
VIN = VIO = 3.6 V
–10
—
10
Low Level Input Current8
IIL
VIN = 0 V,
VIO = 3.6 V
–10
—
10
High Level Output Voltage9
VOH
IOUT = 500 µA
0.8 x VIO
—
—
Low Level Output Voltage9
VOL
IOUT = –500 µA
—
—
0.2 x VIO
Notes:
1. All specifications for the Si4702 unless otherwise noted.
2. Refer to Register 02h, "Power Configuration" on page 24 for ENABLE bit description.
3. The LNA is automatically switched to higher current mode for optimum sensitivity in low SNR conditions.
4. Analog and digital supply currents are simultaneously adjusted based on SNR level.
5. Stereo and RDS functionality are disabled at low SNR levels.
6. RDS functionality only available for Si4703.
7. Refer to Section 4.9. "Reset, Powerup, and Powerdown" on page 19.
8. For input pins SCLK, SEN, SDIO, RST, RCLK, GPIO1, GPIO2, and GPIO3.
9. For output pins SDIO, GPIO1, GPIO2, and GPIO3.
Unit
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
V
V
µA
µA
V
V
Rev. 1.1
5
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