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SI4704-C40 查看數據表(PDF) - Silicon Laboratories

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SI4704-C40
Silabs
Silicon Laboratories Silabs
SI4704-C40 Datasheet PDF : 36 Pages
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Si4704/05-C40
Table 7. SPI Control Interface Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
SCLK Frequency
fCLK
0
2.5
MHz
SCLK High Time
tHIGH
25
ns
SCLK Low Time
tLOW
25
ns
SDIO Input, SEN to SCLKSetup
tS
15
ns
SDIO Input to SCLKHold
SEN Input to SCLKHold
tHSDIO
tHSEN
10
ns
5
ns
SCLKto SDIO Output Valid
SCLKto SDIO Output High Z
tCDV
tCDZ
Read
Read
2
25
ns
2
25
ns
SCLK, SEN, SDIO, Rise/Fall time
tR
tF
10
ns
Note: When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
SCLK 70%
30%
SEN 70%
30%
tS
tS
tR
tF
tHIGH tLOW
tHSDIO
tHSEN
SDIO 70%
30%
C7
C6–C1
C0
D7
D6–D1
D0
Control Byte In
8 Data Bytes In
Figure 6. SPI Control Interface Write Timing Parameters
SCLK 70%
30%
SEN 70%
30%
SDIO 70%
30%
tS
tS
C7
C6–C1
tCDV
tHSDIO
C0
D7
tHSEN
D6–D1
tCDZ
D0
Control Byte In
Bus
Turnaround
16 Data Bytes Out
(SDIO or GPO1)
Figure 7. SPI Control Interface Read Timing Parameters
10
Rev. 1.0

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