SI5322 查看數據表（PDF） - Silicon Laboratories
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SI5322 Datasheet PDF : 16 Pages
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Si5322
Pin #
5, 10, 11,
15, 32
6, 8, 31
9
12
13
14
16
17
Pin Name
VDD
GND
AUTOSEL
CKIN2+
CKIN2–
DBL2_BY
CKIN1+
CKIN1–
Table 3. Si5322 Pin Descriptions (Continued)
I/O Signal Level
Description
Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass
capacitors should be associated with the following VDD pins:
VDD
Supply 5
0.1 µF
10
0.1 µF
32
0.1 µF
A 1.0 µF should be placed as close to device as is practical.
GND
Supply
Ground.
Must be connected to system ground. Minimize the ground
path impedance for optimal performance of this device.
Manual/Automatic Clock Selection.
Three level input that selects the method of input clock
I
3-Level
selection to be used.
L = Manual.
M = Automatic non-revertive.
H = Automatic revertive.
Clock Input 2.
Differential input clock. This input can also be driven with a
I
Multi
single-ended signal. Input frequency selected from a table
of values. The same frequency must be applied to CKIN1
and CKIN2.
Output 2 Disable/Bypass Mode Control.
Controls enable of CKOUT2 divider/output buffer path and
I
3-Level
PLL bypass mode.
L = CKOUT2 enabled.
M = CKOUT2 disabled.
H = Bypass mode with CKOUT2 enabled.
Clock Input 1.
Differential input clock. This input can also be driven with a
I
Multi
single-ended signal. Input frequency selected from a table
of values. The same frequency must be applied to CKIN1
and CKIN2.
Preliminary Rev. 0.47
7
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