SI5324A-C-GM 查看數據表（PDF） - Silicon Laboratories

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SI5324A-C-GM

ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Silicon Laboratories 

Si5324

Table 3. AC Characteristics (Continued)

(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Output Rise/Fall

(20–80 %) @

CKOTRF Output not configured for

—

230

350

ps

CMOS or Disabled

622.08 MHz output

See Figure 2

Output Rise/Fall

(20–80%) @

212.5 MHz output

Output Rise/Fall

(20–80%) @

212.5 MHz output

Output Duty Cycle

Uncertainty @

622.08 MHz

CKOTRF

CMOS Output

—

VDD = 1.71

CLOAD = 5 pF

CKOTRF

CMOS Output

—

VDD = 2.97

CLOAD = 5 pF

CKODC

100  Load

—

Line-to-Line

Measured at 50% Point

(Not for CMOS)

—

8

ns

—

2

ns

—

+/-40

ps

LVCMOS Input Pins

Minimum Reset Pulse

Width

Reset to Microproces-

sor Access Ready

LVCMOS Output Pins

tRSTMN

tREADY

1

µs

10

ms

Rise/Fall Times

tRF

CLOAD = 20pf

—

25

—

ns

See Figure 2

LOSn Trigger Window LOSTRIG From last CKINn to 

—

Internal detection of LOSn

N3 ≠ 1

—

4.5 x N3 TCKIN

Time to Clear LOL after

LOS Cleared

tCLRLOL

LOS to LOL

Fold = Fnew

—

10

—

ms

Stable Xa/XB reference

Notes:

1. Input to output phase skew after an ICAL is not controlled and can assume any value.

2. Lock and settle time performance is dependent on the frequency plan, the XAXB reference frequency, and LOCKT

setting (see application note, “AN803: Lock and Settling Time Considerations for Si5324/27/69/74 Any-Frequency

Jitter Attenuating Clock ICs”. Visit the Silicon Labs Technical Support web page at:

https://www.silabs.com/support/pages/contacttechnicalsupport.aspx to submit a technical support request regarding

the lock time of your frequency plan.

3. LOCKT = 3.3 ms

10

Rev. 1.1

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