SI5324A-C-GM 查看數據表（PDF） - Silicon Laboratories

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SI5324A-C-GM

ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Silicon Laboratories 

Si5324

Table 3. AC Characteristics (Continued)

(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter

Device Skew

Symbol

Test Condition

Min

Typ

Max

Unit

Output Clock Skew

tSKEW

 of CKOUTn to  of

—

—

100

ps

CKOUT_m, CKOUTn

and CKOUT_m at same

frequency and signal

format

PHASEOFFSET = 0

CKOUT_ALWAYS_ON = 1

SQ_ICAL = 1

Phase Change due to

Temperature Variation1

tTEMP

Max phase changes from

–40 to +85 °C

—

300

500

ps

PLL Performance

(fin = fout = 622.08 MHz; BW = 7 Hz; LVPECL, XAXB = 114.285 MHz)

Lock Time2

Si5324E-C-GM3

tLOCKMP Start of ICAL to of LOL

—

1

1.5

s

Si5324A/B/C/D-C-GM

—

0.8

1.0

Settle Time2

Si5324E-C-GM

tSETTLE Start of ICAL to Fout within

—

1.2

1.5

s

5 ppm of final value

Si5324A/B/C/D-C-GM

—

4.2

5.0

Output Clock Phase

Change

Closed Loop Jitter

Peaking

Jitter Tolerance

tP_STEP

JPK

JTOL

After clock switch

f3  128 kHz

—

200

—

0.05

Jitter Frequency Loop 5000/BW

—

Bandwidth

—

ps

0.1

dB

—

ns pk-pk

Notes:

1. Input to output phase skew after an ICAL is not controlled and can assume any value.

2. Lock and settle time performance is dependent on the frequency plan, the XAXB reference frequency, and LOCKT

setting (see application note, “AN803: Lock and Settling Time Considerations for Si5324/27/69/74 Any-Frequency

Jitter Attenuating Clock ICs”. Visit the Silicon Labs Technical Support web page at:

https://www.silabs.com/support/pages/contacttechnicalsupport.aspx to submit a technical support request regarding

the lock time of your frequency plan.

3. LOCKT = 3.3 ms

Rev. 1.1

11

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