SI5324E-C-GM 查看數據表（PDF） - Silicon Laboratories

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SI5324E-C-GM

ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Silicon Laboratories 

Si5324

ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/

JITTER ATTENUATOR

Features

 Generates any frequency from  Freerun, Digital Hold operation

2 kHz to 945 MHz and select

 Configurable signal format per

frequencies to 1.4 GHz from an

output (LVPECL, LVDS, CML,

input frequency of 2 kHz to

CMOS)

710 MHz

 Support for ITU G.709 and custom

 Ultra-low jitter clock outputs as low FEC ratios (255/238, 255/237,

as 290 fs rms (12 kHz–20 MHz),

255/236, 239/237, 66/64, 239/238,

320 fs rms (50 kHz–80 MHz)

15/14, 253/221, 255/238)

 Integrated loop filter with

 LOL, LOS, FOS alarm outputs

selectable loop bandwidth

 I2C or SPI programmable

(4– 525 Hz)

 On-chip voltage regulator with high

 Meets ITU-T G.8251 and Telcordia PSNR

GR-253-CORE jitter specification  Single supply 1.8 ±5%, 2.5 ±10%,

 Hitless input clock switching with

or 3.3 V ±10%

phase build-out

 Small size: 6 x 6 mm 36-lead QFN

 Pb-free, ROHS-compliant

Applications

 Broadcast video –3G/HD/SD-SDI,  1/2/4/8/10G Fibre Channel line

Genlock

cards

 Packet Optical Transport Systems  GbE/10/40/100G Synchronous

(P-OTS), MSPP

Ethernet (LAN/WAN)

 OTN/OTU-1/2/3/4 Asynchronous  Data converter clocking

Demapping (Gapped Clock)

 Wireless base stations

 SONET OC-48/192/768,

 Test and measurement

SDH/STM-16/64/256 line cards

Description

The Si5324 is a low-bandwidth, jitter-attenuating, precision clock multiplier

for applications requiring sub 1 ps jitter performance with loop bandwidths

between 4 Hz and 525 Hz. The Si5324 accepts two input clocks ranging

from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz

to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided

down separately from a common source. The Si5324 can also use its

external reference as a clock source for frequency synthesis. The device

provides virtually any frequency translation combination across this

operating range. The Si5324 input clock frequency and clock multiplication

ratio are programmable via an I2C or SPI interface. The Si5324 is based on

Silicon Laboratories' 3rd-generation DSPLL® technology, which provides

any-frequency synthesis and jitter attenuation in a highly integrated PLL

solution that eliminates the need for external VCXO and filter components.

The DSPLL loop bandwidth is digitally programmable, providing jitter

performance optimization at the application level. The Si5324 is ideal for

providing clock multiplication and jitter attenuation in high performance

timing applications.

Ordering Information:

See page 64.

Pin Assignments

36 35 34 33 32 31 30 29 28

RST 1

27 SDI

NC 2

26 A2_SS

INT_C1B 3

25 A1

C2B 4

VDD 5

XA 6

GND

Pad

24 A0

23 SDA_SDO

22 SCL

XB 7

21 CS_CA

GND 8

20 GND

NC 9

19 GND

10 11 12 13 14 15 16 17 18

Rev. 1.1 1/14

Copyright © 2014 by Silicon Laboratories

Si5324

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