SI5325A-B-GMR 查看數據表（PDF） - Silicon Laboratories

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SI5325A-B-GMR

µP-PROGRAMMABLE PRECISION CLOCK MULTIPLIER

Silicon Laboratories 

Si5325

Table 1. Performance Specifications

(VDD = 1.8, 2.5, or 3.3 V ±10%, TA = –40 to 85 ºC)

Parameter

Symbol

Test Condition

Min

Typ

Max Unit

Temperature Range

TA

Supply Voltage

VDD

–40

25

85

ºC

2.97

3.3

3.63

V

2.25

2.5

2.75

V

1.62

1.8

1.98

V

Supply Current

IDD

fOUT = 622.08 MHz

—

Both CKOUTs enabled

LVPECL format output

251

279

mA

CKOUT2 disabled

—

217

243

mA

fOUT = 19.44 MHz

—

Both CKOUTs enabled

CMOS format output

204

234

mA

CKOUT2 disabled

—

194

220

mA

Tristate/Sleep Mode

—

TBD

TBD

mA

Input Clock Frequency

(CKIN1, CKIN2)

CKF

Input frequency and clock

10

multiplication ratio deter-

—

710 MHz

Output Clock Frequency

(CKOUT1, CKOUT2)

CKOF

mined by programming

device PLL dividers. Consult

10

970

—

945 MHz

—

1134

Silicon Laboratories configu-

ration software DSPLLsim at

1213

—

1417

www.silabs.com/timing to

determine PLL divider set-

tings for a given input fre-

quency/clock multiplication

ratio combination.

Input Clocks (CKIN1, CKIN2)

Differential Voltage Swing CKNDPP

Common Mode Voltage CKNVCM

1.8 V ±10%

2.5 V ±10%

0.25

—

0.9

—

1.0

—

1.9

VPP

1.4

V

1.7

V

3.3 V ±10%

1.1

—

1.95

V

Rise/Fall Time

Duty Cycle

CKNTRF

CKNDC

20–80%

Whichever is less

—

11

ns

40

—

60

%

50

—

—

ns

Output Clocks (CKOUT1, CKOUT2)

Common Mode

Differential Output Swing

Single Ended Output

Swing

VOCM

VOD

VSE

LVPECL

100 Ω load

line-to-line

VDD – 1.42

—

VDD – 1.25 V

1.1

—

1.9

V

0.5

—

0.93

V

Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision

Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.

2

Preliminary Rev. 0.25

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