SI5325B-B-GM 查看數據表（PDF） - Silicon Laboratories
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SI5325B-B-GM Datasheet PDF : 16 Pages
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Si5325
VDD = 3.3 V
System
Power
Supply
Ferrite
Bead
C4 1 µF
C3 0.1 µF
C2 0.1 µF
C1 0.1 µF
130 Ω
82 Ω
130 Ω
CKIN1+
82 Ω
CKIN1–
Input
Clock
Sources*
VDD = 3.3 V
130 Ω
130 Ω
CKIN2+
82 Ω
82 Ω
CKIN2–
CKOUT1+
CKOUT1–
CKOUT2+
CKOUT2–
Si5325
INT_C1B
C2B
0.1 µF
+
100 Ω
–
0.1 µF
0.1 µF
+
100 Ω
–
0.1 µF
Clock Outputs
Interrupt/CKIN_1 Invalid Indicator
CKIN_2 Invalid Indicator
Control Mode (L)
Reset
CMODE
RST
A[2:0]
SDA
SCL
Serial Port Address
Serial Data
I2C Interface
Serial Clock
*Note: Assumes differential LVPECL termination (3.3 V) on clock inputs.
Figure 2. Si5325 Typical Application Circuit (I2C Control Mode)
VDD = 3.3 V
System
Power
Supply
Ferrite
Bead
C4 1 µF
C3 0.1 µF
C2 0.1 µF
C1 0.1 µF
130 Ω
82 Ω
130 Ω
CKIN1+
82 Ω
CKIN1–
Input
Clock
Sources*
VDD = 3.3 V
130 Ω
130 Ω
82 Ω
82 Ω
CKIN2+
CKIN2–
CKOUT1+
CKOUT1–
CKOUT2+
CKOUT2–
Si5325
INT_C1B
C2B
0.1 µF
+
100 Ω
–
0.1 µF
0.1 µF
+
100 Ω
–
0.1 µF
Clock Outputs
Interrupt/CLKIN_1 Invalid Indicator
CLKIN_2 Invalid Indicator
Control Mode (H)
Reset
CMODE
RST
SS
SDO
SDI
Slave Select
Serial Data Out
Serial Data In
SPI Interface
SCLK
Serial Clock
*Note: Assumes differential LVPECL termination (3.3 V) on clock inputs.
Figure 3. Si5325 Typical Application Circuit (SPI Control Mode)
Preliminary Rev. 0.25
5
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