SI5326 查看數據表（PDF） - Silicon Laboratories

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SI5326

ANY FREQUENCY PRECISION CLOCK MULTIPLIER / JITTER ATTENUATOR

Silicon Laboratories 

Si5326

Table 3. Microprocessor Control (Continued)

(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter

SPI Specifications

Symbol

Test Condition

Duty Cycle, SCLK

tDC

SCLK = 10 MHz

Cycle Time, SCLK

tc

Rise Time, SCLK

tr

Fall Time, SCLK

tf

20–80%

20–80%

Low Time, SCLK

tlsc

High Time, SCLK

thsc

Delay Time, SCLK Fall

td1

to SDO Active

Delay Time, SCLK Fall

td2

to SDO Transition

Delay Time, SS Rise

td3

to SDO Tri-state

Setup Time, SS to

tsu1

SCLK Fall

Hold Time, SS to

th1

SCLK Rise

Setup Time, SDI to

tsu2

SCLK Rise

Hold Time, SDI to

th2

SCLK Rise

Delay Time between

tcs

Slave Selects

20–20%

80–80%

Min

Typ

Max

Unit

40

—

60

%

100

—

—

ns

—

—

25

ns

—

—

25

ns

30

—

—

ns

30

—

—

ns

—

—

25

ns

—

—

25

ns

—

—

25

ns

25

—

—

ns

20

—

—

ns

25

—

—

ns

20

—

—

ns

25

—

—

ns

10

Rev. 1.0

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