SI5325/26-EVB 查看數據表（PDF） - Silicon Laboratories

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SI5325/26-EVB

ANY FREQUENCY PRECISION CLOCK MULTIPLIER / JITTER ATTENUATOR

Silicon Laboratories 

Si5326

Table 4. AC Specifications

(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Single-Ended Reference Clock Input Pin XA (XB with cap to GND)

Input Resistance

XARIN RATE[1:0] = LM, ML, MH,

—

12

—

k

or HM, ac coupled

Input Voltage Swing

XAVPP RATE[1:0] = LM, ML, MH,

0.5

—

1.2

VPP

or HM, ac coupled

Differential Reference Clock Input Pins (XA/XB)

Input Voltage Swing

XA/XBVPP RATE[1:0] = LM, ML, MH,

0.5

—

1.2

VPP,

or HM

each.

CKINn Input Pins

Input Frequency

Input Duty Cycle

(Minimum Pulse

Width)

CKNF

0.002

—

CKNDC

Whichever is smaller

40

—

(i.e., the 40% / 60%

limitation applies only

to high frequency

clocks)

2

—

710

MHz

60

%

—

ns

Input Capacitance

CKNCIN

Input Rise/Fall Time

CKNTRF

20–80%

See Figure 2

CKOUTn Output Pins

(See ordering section for speed grade vs frequency limits)

Output Frequency

(Output not config-

ured for CMOS or

Disabled)

CKOF

N1  6

N1 = 5

N1 = 4

—

—

3

pF

—

—

11

ns

0.002

—

945

MHz

970

—

1134

MHz

1.213

—

1.4

GHz

Maximum Output

CKOF

—

Frequency in CMOS

Format

Output Rise/Fall

(20–80 %) @

CKOTRF Output not configured for

—

CMOS or Disabled

622.08 MHz output

See Figure 2

Output Rise/Fall

CKOTRF

CMOS Output

—

(20–80%) @

VDD = 1.71

212.5 MHz output

CLOAD = 5 pF

—

212.5

MHz

230

350

ps

—

8

ns

Rev. 1.0

11

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