SI5328 查看數據表（PDF） - Silicon Laboratories

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SI5328

ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Silicon Laboratories 

Si5328

Table 2. DC Characteristics (Continued)

(VDD = 2.5 V ±10% or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter

3-Level Input Pins4

Symbol

Test Condition

Input Voltage Low

VILL

Input Voltage Mid

VIMM

Input Voltage High

VIHH

Input Low Current

IILL

Input Mid Current

IIMM

Input High Current

IIHH

LVCMOS Output Pins

See Note 4

See Note 4

See Note 4

Min

Typ

Max

Unit

—

0.45 x

VDD

0.85 x

VDD

–20

–2

—

—

0.15 x VDD

V

—

0.55 x VDD

V

—

—

V

—

—

µA

—

+2

µA

—

20

µA

Output Voltage Low

VOL

IO = 2 mA

VDD = 2.25 V

—

—

0.4

V

Output Voltage Low

IO = 2 mA

VDD = 2.97 V

—

—

0.4

V

Output Voltage High

VOH

IO = –2 mA

VDD = 2.25 V

VDD –0.4

—

—

V

Output Voltage High

IO = –2 mA

VDD = 2.97 V

VDD –0.4

—

—

V

Disabled Leakage

IOZ

Current

RSTb = 0

–100

—

100

µA

Notes:

1. Current draw is independent of supply voltage

2. No under- or overshoot is allowed.

3. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 312.5 MHz.

4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family

Reference Manual for more details.

8

Rev. 1.0

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