SL74HC175 查看數據表（PDF） - System Logic Semiconductor

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SL74HC175

Quad D Flip-Flop with Common Clock and Reset

System Logic Semiconductor 

SL74HC175

Quad D Flip-Flop with

Common Clock and Reset

High-Performance Silicon-Gate CMOS

The SL74HC175 is identical in pinout to the LS/ALS175. The device

inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LS/ALSTTL outputs.

This device consists of four D flip-flops with common Reset and

Clock inputs, and separate D inputs. Reset (active-low) is

asynchronous and occurs when a low level is applied to the Reset

input. Information at a D input is transferred to the corresponding Q

output on the next positive-going edge of the Clock input.

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

ORDERING INFORMATION

SL74HC175N Plastic

SL74HC175D SOIC

TA = -55° to 125° C for all packages

PIN ASSIGNMENT

LOGIC DIAGRAM

PIN 16=VCC

PIN 8 = GND

FUNCTION TABLE

Inputs

Outputs

Reset Clock

D

QQ

L

X

X

LH

H

H

HL

H

L

LH

H

L

X no change

X = Don’t care

SLS

System Logic

Semiconductor

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