SM5844 查看數據表（PDF） - Nippon Precision Circuits
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SM5844 Datasheet PDF : 26 Pages
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SM5844AF
Microcontroller Interface (MCOM, MDT, MCK, MLEN)
When MCOM is HIGH, MDT (data), MCK (clock)
and MLEN (latch enable clock) interface pins are
used.
Input data on MDT is synchronized to the MCK
clock. Data is read into the input stage shift register
on the rising edge of MCK. Accordingly, the input
data should change on the falling edge of MCK.
Input data enters an internal SIPO (serial-to-parallel
converter register), and then the parallel data is
latched into the mode register on the rising edge of
the latch enable clock MLEN.
The mode register addressed is determined by the 1st
bit of the 12 data bits before MLEN goes HIGH. If
this bit is LOW, then the data is read into the
attenuation data register as shown in figure 1. If this
bit is HIGH, then the data is read into the mode flag
register as shown in figure 2. The function of each bit
in the mode flag register is described in table 1.
MDT
MCK
B1
B2
B3
B4
LOW
a0
a1
a2
MSB
B8
B9
B10
B11
B12
a6
a7
a8
a9
a10
LSB
MLEN
MDT
MCK and MLEN can also follow the dotted lines.
Figure 1. Attenuation data format (B1 = LOW)
B1
HIGH
B2 * * B5
Not used
B6
FTST1
B7
FTST2
B8
FRATE
B9
F12DB
B10
FFSI1
B11
FFSI2
B12
FDEEM
MCK
MLEN
MCK and MLEN can also follow the dotted lines.
Figure 2. Mode flag data format (B1 = HIGH)
NIPPON PRECISION CIRCUITS—13
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