SM5844 查看數據表（PDF） - Nippon Precision Circuits

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SM5844

Asynchronous Sample Rate Converter

Nippon Precision Circuits  

SM5844AF

Internal Arithmetic Timing Auto-reset

The clock on LRCI should pass through 1 cycle for

every 384 (ICKSL = HIGH) or 256 (ICKSL = LOW)

ICLK clock cycles to maintain correct internal

arithmetic sequence. If the number of ICLK cycles is

different, increases or decreases, or any jitter is

present, device operation could be affected.

There is a fixed-value tolerance within which the

internal sequence and LRCI clock timing are not

adversely affected.

Table 13. Clock tolerance

ICKSL

HIGH (384fs mode)

LOW (256fs mode)

Allowable clock variation

+8/−6 cycles

+4/−3 cycles

Whenever the allowable tolerance is exceeded, the

internal sequence is automatically reset so that the

internal sequence matches the LRCI clock. When

this occurs, there is a possibility that click noise will

be generated.

Output Timing Calculation

The output timing is calculated to maintain the

desired ratio between the output data cycle and the

input data cycle.

Filter Characteristic Selection

Conversion rates from 0.5 to 2.0 times are supported

using the following 4 filter types.

The ratio between the output sample rate and input

sample rate is measured automatically and the most

suitable filter type for this ratio is selected

automatically.

Table 15. fs ratio and filter selection

Mode

1

2

3

4

Filter

Up converter

48.0 to 44.1 kHz

44.1 to 32.0 kHz

48.0 to 32.0 kHz

fs ratio (fso/fsi)

1.0 to 2.0

0.91875

0.72562

0.66667

Selects range

≥ 0.97

0.865 to 0.97

0.711 to 0.865

≤ 0.711

Output Format Control (OW18N,

OW20N, IISN)

The output is in MSB-first, 2s-complement, L/R

alternating, bit serial format with a continuous bit

clock.

Table 14. Output format selection

Mode

Inputs

Output format

IISN

OW20N OW18N

W ord

length

IIS

selection

Front/rear

packing

1

HIGH HIGH 16 bits

2

HIGH LOW 18 bits

Rear

HIGH

Non IIS

3

LOW HIGH 20 bits

4

LOW LOW 20 bits

5

HIGH HIGH 16 bits

Front

6 LOW HIGH LOW 18 bits IIS

7

LOW

× 20 bits

When the selected fs conversion ratio and the actual

sample rate conversion ratio do not coincide, the

following phenomenon are generated.

Table 16. fs ratio mismatch

Condition

Actual sample rate conversion

ratio is low er than the selected

filter conversion ratio

Actual sample rate conversion

ratio is higher than the selected

filter conversion ratio

Affect

The audio band high-pass

develops aliasing noise.

The audio band high-pass is cut

off.

Note: An output noise may be generated if the fs conversion ratio

changes at a rate greater than 0.057%/sec.

NIPPON PRECISION CIRCUITS—19

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