SM8222A 查看數據表（PDF） - Nippon Precision Circuits
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SM8222A Datasheet PDF : 15 Pages
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SM8222A/B
PIN DESCRIPTION
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Name
TIP
RING
GS
AGND
CAP
RDIN
RDRC
RDET
MODE
OSCIN
OSCOUT
GND
IC
PDWN
15
FSKEN
16
DCLK
17
DOUT
18
DR
19
CDET
20
INT
21
STD
22
EST
23
STGT
24
VDD
I/O
Description
I
Tip input: Connected to the telephone through a protection circuit.
I
Ring input: Connected to the telephone through a protection circuit.
O
Input stage amplifier output: Used to select the input amplifier gain
O
Analog ground: Internal reference voltage (VDD/2) output.
I
Reference voltage capacitor connection. C = 0.1 µF
I
Ring detect input: Line reversal and ring signal detect input. Connect to detect attenuated ring
signals. Schmitt-trigger input.
I/O
Ring detect RC connection: RC network connection to set the ring detect delay time. Open-drain
output and schmitt-trigger input.
O
Ring detect output: RDRC schmitt-trigger buffer output. LOW when a ring signal is detected.
FSK interface mode select: Demodulated FSK signal output method select.
I
LOW [Mode = 0]: Demodulated data output and data sync clock output.
HIGH [Mode = 1]: Data output in sync with an external clock.
I
Crystal oscillator element input: Oscillator element connection between OSCIN and OSCOUT.
O
Crystal oscillator element output: Oscillator element connection between OSCIN and OSCOUT.
–
Ground: Connect to system ground.
I
Test input: Tie LOW for normal operation.
Power-down control: LOW for normal operation. HIGH for device power-down state.When device is
I
powered-down, AGND, OSCOUT, DCLK, DOUT, INT, CDET are all HIGH. DR also goes HIGH in
mode 0 output. Schmitt-trigger input.
FSK signal output control: Demodulated FSK signal output and carrier detect output control.
Mode 0: DCLK, DOUT, DR, CDET control
I
Mode 1: DCLK, DOUT, CDET control
FSK signal reception enabled when HIGH.
Signal pins (above) go HIGH when FSKEN is LOW.
FSK interface clock: Demodulated FSK signal output clock.
I/O Mode 0: Clock output in sync with data
Mode 1: Data read clock input
O
Data output: Demodulated FSK signal output. HIGH-level output when PDWN is HIGH or FSKEN is
LOW, or when CDET is HIGH in receive state.
O
Data output trigger: Demodulated FSK data timing output. Active-LOW. Becomes active when 8 bits
of data are completed.
O
Carrier (FSK signal) detect output: Goes LOW when a valid carrier signal is detected.
O
Interrupt signal output: Goes LOW when either RDET is LOW, DR is LOW or STD is HIGH.
O
Dual tone indicator output: Goes HIGH if the dual tone detect signal is recognized after the external
RC circuit time delay has elapsed.
O
Dual tone detect output: Goes HIGH when the dual tone is detected.
I/O
Dual tone RC time constant circuit connection: External RC network connection for dual tone signal
detection processing. Sets STD output.
–
Supply voltage
NIPPON PRECISION CIRCUITS—3
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