SN54-74LS168 查看數據表（PDF） - ON Semiconductor

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SN54-74LS168

BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS

ON Semiconductor 

SN54/74LS168 • SN54/74LS169

CP 1.3 V

Q OR TC

AC WAVEFORMS

1/fmax

tW

CET

1.3 V

1.3 V

tPHL

tPLH

TC

1.3 V

1.3 V

1.3 V

tPLH

1.3 V

1.3 V

tPHL

1.3 V

Figure 1. Clock to Output Delays,

Count Frequency, and Clock Pulse Width

Figure 2. Count Enable Trickle Input

To Terminal Count Output Delays

CP

ts(H)

1.3 V

th(H) = 0 ts(L)

1.3 V

th(L) = 0

CP

1.3 V

1.3 V

1.3 V

P0 • P1 • P2 • P3 1.3 V

1.3 V 1.3 V

1.3 V

tPLH

tPHL

TC

1.3 V

1.3 V

Q0 • Q1 • Q2 • Q3

Figure 3. Clock to Terminal Delays

Figure 4. Setup Time (ts) and Hold (th)

for Parallel Data Inputs

CP

ts(L)

SR OR PE 1.3 V

1.3 V

th(L) = 0

1.3 V

ts(H)

1.3 V

1.3 V

th(H) = 0

1.3 V

CP

ts(H)

CEP 1.3 V

ts(H)

CET 1.3 V

1.3 V

th(H) = 0 ts(L)

1.3 V 1.3 V

th(H) = 0

1.3 V

1.3 V

th(L) = 0

1.3 V

ts(L)

1.3 V

1.3 V

th(L) = 0

1.3 V

The shaded areas indicate when the

input is permitted to change for

predictable output performance.

Figure 5. Setup Time and Hold Time for

Count Enable and Parallel Enable Inputs,

and Up-Down Control Inputs

U/D

tPLH

TC

1.3 V

1.3 V

1.3 V

tPHL

1.3 V

Figure 6. Up-Down Input to

Terminal Count Output Delays

FAST AND LS TTL DATA

5-6

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