SN54-74LS192 查看數據表（PDF） - Motorola => Freescale

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SN54-74LS192

PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER

Motorola => Freescale 

SN54/74LS192 • SN54/74LS193

AC SETUP REQUIREMENTS (TA = 25°C)

Symbol

tW

ts

th

trec

Parameter

Any Pulse Width

Data Setup Time

Data Hold Time

Recovery Time

Limits

Min Typ Max Unit

20

ns

20

ns

5.0

ns

40

ns

Test Conditions

VCC = 5.0 V

DEFINITIONS OF TERMS

SETUP TIME (ts) is defined as the minimum time required for

the correct logic level to be present at the logic input prior to the

PL transition from LOW-to-HIGH in order to be recognized and

transferred to the outputs.

HOLD TIME (th) is defined as the minimum time following the

PL transition from LOW-to-HIGH that the logic level must be

maintained at the input in order to ensure continued recogni-

tion. A negative HOLD TIME indicates that the correct logic

level may be released prior to the PL transition from

LOW-to-HIGH and still be recognized.

RECOVERY TIME (trec) is defined as the minimum time

required between the end of the reset pulse and the clock

transition from LOW-to-HIGH in order to recognize and

transfer HIGH data to the Q outputs.

FAST AND LS TTL DATA

5-6

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