SN74LS73A 查看數據表（PDF） - Motorola => Freescale

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SN74LS73A

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

Motorola => Freescale 

SN54 / 74LS73A

AC WAVEFORMS

J or K *

CP

Q

Q

ts(L)

1.3 V

th(L) = 0

tW(L)

tPHL

1.3 V

1.3 V

ts(H)

th(H) = 0

1.3 V

1

fMAX

tW(H)

1.3 V

tPLH

1.3 V

tPLH

tPHL

1.3 V

1.3 V

*The shaded areas indicate when the input is permitted to change for predictable output performance.

Figure 1. Clock to Output Delays, Data

Set-Up and Hold Times, Clock Pulse Width

SET

CLEAR

Q

Q

tW

1.3 V

1.3 V

tPLH

1.3 V

tPHL

1.3 V

tW

1.3 V

1.3 V

tPHL

1.3 V

tPLH

1.3 V

Figure 2. Set and Clear to Output Delays,

Set and Clear Pulse Widths

FAST AND LS TTL DATA

5-70

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