UT61L5128(2002) 查看數據表（PDF） - Utron Technology Inc
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UT61L5128 Datasheet PDF : 10 Pages
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UTRON
Preliminary Rev. 1.1
UT61L5128
512K X 8 BIT HIGH SPEED CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2,4)
tRC
Address
tAA
tOH
tOH
Dout
Data Valid
READ CYCLE 2 ( CE , and OE Controlled) (1,3,5,6)
Address
CE
OE
Dout
HIGH-Z
t RC
t AA
t ACE
t CLZ
t OLZ
t OE
t CHZ
t OHZ
t OH
Data Valid
HIGH-Z
Notes :
1. WE is HIGH for a read cycle.
2. Device is continuously selected CE =VIL .
3. Address must be valid prior to or coincident with CE transition; otherwise tAA is the limiting parameter.
4. OE is low.
5. tCLZ, tOLZ, tCHZ and tOHZ are specified with CL=5pF. Transition is measured ±500mV from steady state.
6. At any given temperature and voltage condition, tCHZ is less than tCLZ, tOHZ is less than tOLZ.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
P80061
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