MX29L3211MC-10 查看數據表（PDF） - Macronix International

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MX29L3211MC-10

32M-BIT [4M x 8/2M x 16] CMOS SINGLE VOLTAGE PAGEMODE FLASH EEPROM

Macronix International 

MX29L3211

READ/RESET COMMAND

The read or reset operation is initiated by writing the

read/reset command sequence into the command

register. Microprocessor read cycles retrieve array data

from the memory. The device remains enabled for reads

until the CIR contents are altered by a valid command

sequence.

The device will automatically power-up in the read/reset

state. In this case, a command sequence is not required

for "read operation". Standard microprocessor read

cycles will retrieve array data. This default value ensures

that no spurious alteration of the memory content occurs

during the power transition. Refer to the AC Read

Characteristics and Waveforms for the specific timing

parameters.

The MX29L3211 is accessed like an EPROM. When CE

and OE are low and WE is high the data stored at the

memory location determined by the address pins is

asserted on the outputs. The outputs are put in the high

impedance state whenever CE or OE is high. This dual

line control gives designers flexibility in preventing bus

contention.

Note that the read/reset command is not valid when

program or erase is in progress.

PAGE READ

The MX29L3211 offers "fast page mode read" function.

The users can take the access time advantage if keeping

CE, OE at low and the same page address (A3~A20

unchanged). Please refer to Figure 5-2 for detailed

timing waveform. The system performance could be

enhanced by initiating 1 normal read and 7 fast page

reads(for word mode A0~A2) or 15 fast page reads(for

byte mode altering A-1~A2).

PAGE PROGRAM

To initiate Page Program mode, a three-cycle command

sequence is required. There are two "unlock" write

cycles. These are followed by writing the page program

command-A0H.

Any attempt to write to the device without the three-cycle

command sequence will not start the internal Write State

Machine(WSM), no data will be written to the device.

After three-cycle command sequence is given, a

byte(word) load is performed by applying a low pulse on

the WE or CE input with CE or WE low (respectively) and

OE high. The address is latched on the falling edge of

CE or WE, whichever occurs last. The data is latched by

the first rising edge of CE or WE. Maximum of 128 words

of data may be loaded into each page by the same

procedure as outlined in the page program section

below.

BYTE-WIDE LOAD/WORD-WIDE LOAD

BYTE(word) loads are used to enter the 128 words(256

bytes) of a page to be programmed or the software

codes for data protection. A byte(word load) is performed

by applying a low pulse on the WE or CE input with CE

or WE low (respectively) and OE high. The address is

latched on the falling edge of CE or WE, whichever

occurs last. The data is latched by the first rising edge

of CE or WE.

Either word-wide load or byte-wide load is

determined(BYTE = VIL or VIH is latched) on the falling

edge of the WE (or CE) during the 3rd command write

cycle.

PROGRAM

Any page to be programmed should have the page in the

erased state first, i.e. performing sector erase is

suggested before page programming can be performed.

The device is programmed on a page basis. If a

byte(word) of data within a page is to be changed, data

for the entire page can be loaded into the device. Any

byte(word) that is not loaded during the programming of

its page will be still in the erased state (i.e. FFH). Once

the bytes of a page are loaded into the device, they are

simultaneously programmed during the internal

programming period. After the first data byte (word) has

been loaded into the device, successive byte(word) are

entered in the same manner. Each new byte(word) to

be programmed must have its high to low transition on

WE (or CE) within 30us of the low to high transition of WE

(or CE) of the preceding byte(word). A7 to A20 specify

the page address, i.e., the device is page-aligned on 128

word(256 byte)boundary. The page address must be

valid during each high to low transition of WE or CE. A-

1 to A6 specify the byte address within the page, A0 to

P/N:PM0641

REV. 0.3, NOV. 06, 2001

9

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