UT61L256LS-15 查看數據表（PDF） - Utron Technology Inc
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UT61L256LS-15 Datasheet PDF : 10 Pages
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Rev. 1.3
UTRON
UT61L256
32K X 8 BIT HIGH SPEED LOW VCC CMOS SRAM
FEATURES
Fast access time : 8/10/12/15ns (max.)
Low operating power consumption:
60 mA (typical.)
Single 3.3V power supply
All inputs and outputs are TTL compatible
Fully static operation
Three state outputs
Package : 28-pin 300 mil SOJ
28-pin 8mm×13.4 mm STSOP
FUNCTIONAL BLOCK DIAGRAM
A4
A3
A14
.
A13
ROW
. A12
DECODER
A7
A6
.
A5
A8
I/O1
...
... I/O
CONTROL
I/O8
...
MEMORY ARRAY
512 ROWS × 512 COLUMNS
. ..
COLUMN I/O
COLUMN DECODER
CE
LOGIC
WE CONTROL
OE
A11 A9 A10 A2 A1 A0
VCC
VSS
PIN DESCRIPTION
SYMBOL
A0 - A14
I/O1 - I/O8
CE
WE
OE
VCC
VSS
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Power Supply
Ground
GENERAL DESCRIPTION
The UT61L256 is a 262,144-bit high speed CMOS
static random access memory organized as
32,768 words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.
The UT61L256 is designed for high-speed system
application. It is particularly suited for use in high
speed and high density system applications.
The UT61L256 operates from a signal 3.3V power
supply and all inputs and outputs are fully TTL
compatible
PIN CONFIGURATION
A14
1
A12
2
A7
3
A6
4
A5
5
A4
6
A3
7
A2
8
A1
9
A0
10
I/O1
11
I/O2
12
I/O3
13
Vss
14
28
Vcc
27
WE
26
A13
25
A8
24
A9
23
A11
22
OE
21
A10
20
CE
19
I/O8
18
I/O7
17
I/O6
16
I/O5
15
I/O4
SOJ
OE
1
A11
2
28
A10
27
CE
A9
3
A8
4
26
I/O8
25
I/O7
A13
5
24
I/O6
WE
6
23
I/O5
Vcc
7
22
I/O4
A14
8
UT61L256
21
Vss
A12
9
A7
10
A6
11
20
I/O3
19
I/O2
18
I/O1
A5
12
17
A0
A4
13
16
A1
A3
14
15
A2
STSOP
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
P80023
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