83C196KB 查看數據表（PDF） - Intel

零件编号

产品描述 (功能)

生产厂家

83C196KB

Advanced 16-bit CHMOS microcomputer ROMless

Intel 

AUTOMOTIVE 8XC196KB

PIN DESCRIPTIONS

Symbol

Name and Function

VCC

VSS

VREF

Main Supply Voltage (a5V)

Digital Circuit Ground (0V) There are three VSS pins all of which MUST be connected

Reference for the A D Converter (a5V) VREF is also the supply voltage to the analog portion

of the A D converter and the logic used to read Port 0 Must be connected for A D and Port 0

to function

ANGND

VPP

XTAL1

Reference Ground for the A D Converter Must be held at nominally the same potential as

VSS

Programming Voltage for the EPROM Parts It should be a12 75V for programming This pin

was VBB on 8X9X-90 parts It is also the timing pin for the return from powerdown circuit

Connect this pin with a 1 mF capacitor to VSS and a 1 MX resistor to VCC If this function is not

used VPP may be tied to VCC

Input of the Oscillator Inverter and the Internal Clock Generator

XTAL2

Output of the Oscillator Inverter

CLKOUT

Output of the Internal Clock Generator The frequency of CLKOUT is the oscillator

frequency It has a 50% duty cycle

RESET

Reset Input to the Chip Input low for at least 4 state times will reset the chip The subsequent

low to high transition resynchronizes CLKOUT and commences a 10-state time sequence in

which the PSW is cleared a byte is read from 2018H loading the CCB and a jump to location

2080H is executed Input high for normal operation RESET has an internal pullup

BUSWIDTH

NMI

Input for Bus Width Selection If CCR bit 1 is a one this pin selects the buswidth for the bus

cycle in progress If BUSWIDTH is low an 8-bit cycle occurs If BUSWIDTH is high a 16-bit

cycle occurs If CCR bit 1 is a 0 the bus is always an 8-bit bus This pin is the TEST pin on the

8X9X-90 parts Systems with TEST tied to VCC need NOT change

A positive transition causes an interrupt vector through external memory location 203EH

INST

Output High during an External Memory Read Indicates the read is an instruction fetch INST

is valid throughout the bus cycle INST is active only during external memory fetches during

internal EPROM ROM fetches INST is held low

EA

Input for Memory Select (External Access) EA equal to a TTL-high causes memory accesses

to locations 2000H through 3FFFH to be directed to on-chip EPROM ROM EA equal to a

TTL-low causes accesses to these locations to be directed to off-chip memory EA e

a12 75V causes execution to begin in the Programming Mode EA has an internal pulldown

so it defaults to execute from external memory unless otherwise driven EA is latched at

reset

ALE ADV

Address Latch Enable or Address Valid Output as Selected by CCR Both pin options provide

a latch to demultiplex the address from the address data bus When the pin is ADV it goes

inactive (high) at the end of the bus cycle ADV can be used as a chip select for external

memory ALE ADV is active only during external memory accesses

5

Share Link: