SN74LS165 查看數據表（PDF） - ON Semiconductor
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SN74LS165 Datasheet PDF : 8 Pages
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SN74LS165
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC CP2 P3 P2 P1 P0 DS Q7
16 15 14 13 12 11 10 9
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual InĆLine Package.
123
PL CP1 P4
4 56
P5 P6 P7
78
Q7 GND
PIN NAMES
CP1, CP2
DS
PL
P0 - P7
Q7
Q7
Clock (LOW-to-HIGH Going Edge) Inputs
Serial Data Input
Asynchronous Parallel Load (Active LOW) Input
Parallel Data Inputs
Serial Output from Last State
Complementary Output
NOTES:
ąa) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
LOADING (Note a)
HIGH
LOW
0.5 U.L.
0.5 U.L.
1.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.75 U.L.
0.25 U.L.
5 U.L.
5 U.L.
LOGIC SYMBOL
1 11 12 13 14 3 4 5 6
10
PL
DS
P0 P1
P2
P3 P4
P5 P6
P7
Q7
9
2
15
CP
Q7
7
VCC = PIN 16
GND = PIN 8
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