SN74LS175ML2 查看數據表（PDF） - ON Semiconductor

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SN74LS175ML2

Quad D Flip-Flop

ON Semiconductor 

SN74LS175

CONNECTION DIAGRAM DIP (TOP VIEW)

VCC Q3 Q3 D3 D2 Q2 Q2 CP

16 15 14 13 12 11 10 9

NOTE:

The Flatpak version has the same

pinouts (Connection Diagram) as

the Dual In-Line Package.

1 2 3 4 56 78

MR Q0 Q0 D0 D1 Q1 Q1 GND

PIN NAMES

D0 – D3

CP

MR

Q0 – Q3

Q0 – Q3

Data Inputs

Clock (Active HIGH Going Edge) Input

Master Reset (Active LOW) Input

True Outputs

Complemented Outputs

NOTES:

a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.

LOADING (Note a)

HIGH

LOW

0.5 U.L.

0.5 U.L.

0.5 U.L.

10 U.L.

10 U.L.

0.25 U.L.

0.25 U.L.

0.25 U.L.

5 U.L.

5 U.L.

LOGIC SYMBOL

4

5

12

13

D0

D1

D2

D3

9

CP

1

MR

Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3

MR CP D3

1 9 13

3 2 6 7 11 10 14 15

VCC = PIN 16

GND = PIN 8

LOGIC DIAGRAM

D2

D1

D0

12

5

4

DQ

CP Q

CD

DQ

CP Q

CD

DQ

CP Q

CD

DQ

CP Q

CD

14

15

Q3 Q3

11

10

Q2 Q2

VCC = PIN 16

GND = PIN 8

= PIN NUMBERS

6

7

Q1 Q1

3

2

Q0 Q0

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