SN74LS156DR2 查看數據表（PDF） - ON Semiconductor

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SN74LS156DR2

Dual 1-of-4 Decoder/Demultiplexer

ON Semiconductor 

SN74LS156

CONNECTION DIAGRAM DIP (TOP VIEW)

VCC Eb Eb A0 O3b O2b O1b O0b

16 15 14 13 12 11 10 9

NOTE:

The Flatpak version has the same

pinouts (Connection Diagram) as

the Dual InĆLine Package.

1 2 3 4 56 78

Ea Ea A1 O3a O2a O1a O0a GND

PIN NAMES

A0, A1

Ea, Eb

Ea

O0 - O3

Address Inputs

Enable (Active LOW) Inputs

Enable (Active HIGH) Input

Active LOW Outputs

LOADING (Note a)

HIGH

LOW

0.5 U.L.

0.5 U.L.

0.5 U.L.

10 U.L.

0.25 U.L.

0.25 U.L.

0.25 U.L.

5 U.L.

NOTES:

ąa) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.

LOGIC SYMBOL

12

13 3

14 15

E

A0

DECODER a A1

012 3

A0

E

A1 DECODER b

0 123

765 4

9 10 11 12

VCC = PIN 16

GND = PIN 8

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