SL74HC4052 查看數據表（PDF） - System Logic Semiconductor

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SL74HC4052

Analog Multiplexer/Demultiplexer High-Performance Silicon-Gate CMOS

System Logic Semiconductor 

SL74HC4052

MAXIMUM RATINGS*

Symbol

VCC

VEE

VIS

VIN

I

PD

Tstg

TL

Parameter

Positive DC Supply Voltage (Referenced to GND)

(Referenced to VEE)

Negative DC Supply Voltage (Referenced to GND)

Analog Input Voltage

Digital Input Voltage (Referenced to GND)

DC Input Current Into or Out of Any Pin

Power Dissipation in Still Air, Plastic DIP+

SOIC Package+

Storage Temperature

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

Value

Unit

-0.5 to +7.0

V

-0.5 to +14.0

-7.0 to +0.5

V

VEE - 0.5 to VCC+0.5

V

-1.5 to VCC +1.5

V

±25

mA

750

mW

500

-65 to +150

°C

260

°C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min Max Unit

VCC

Positive Supply Voltage (Referenced to GND)

(Referenced to VEE)

2.0

6.0

V

2.0 12.0

VEE

Negative DC Supply Voltage (Referenced to GND)

- 6.0 GND

V

VIS

Analog Input Voltage

VEE

VCC

V

VIN

Digital Input Voltage (Referenced to GND)

GND VCC

V

VIO*

Static or Dynamic Voltage Across Switch

-

1.2

V

TA

Operating Temperature, All Package Types

-55 +125

°C

tr, tf

Input Rise and Fall Time (Channel Select VCC =2.0 V

or Enable Inputs)

VCC =4.5 V

VCC =6.0 V

0

1000

ns

0

500

0

400

* For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn;

i. e., the current out of the switch may contain both VCC and switch input components. The reliability of the

device will be unaffected unless the Maximum Ratings are exceeded.

This device contains protection circuitry to guard against damage due to high static voltages or electric

fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated

voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range

indicated in the Recommended Operating Conditions..

Unused digital input pins must be tied to an appropriate logic voltage level (e.g., either GND or VCC).

Unused Analog I/O pins may be left open or terminated.

SLS

System Logic

Semiconductor

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