CXD1812 查看數據表（PDF） - Sony Semiconductor
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CXD1812 Datasheet PDF : 56 Pages
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CXD1812Q/R
2-2. DRAM Interface
(1) Read
Tras
Trp
XRAS
Trcd
Tcas
Tpc
XCAS
Tasr
Tasc
MA0 to MA9
row
col
col
col
row
MDB0 to 7
Trah
Tcah
XMWR
Tids Tidh
high
(2) Write
Tras
Trp
XRAS
XCAS
Trcd
Tcas
Tpc
Tasr
Tasc
MA0 to MA9
row
col
col
col
row
MDB0 to 7
XMWR
Trah
Item
RAS pulse width
RAS precharge width
RAS – CAS delay time
CAS pulse width
Page mode cycle time
Row address setup time (for RAS ↓)
Row address hold time (for RAS ↓)
Column address setup time (for CAS ↓)
Column address hold time (for CAS ↓)
Input data setup time (for CAS ↑)
Input data hold time (for CAS ↑)
Data output setup time (for CAS ↓)
Data output float time (for CAS ↓)
Tcah
Tdos Tdof
Symbol
Min.
Typ.
Tras
3Tw
Trp
2Tw
Trcd
2Tw
Tcas
Tw
Tpc
2Tw
Tasr
Tw – 7
Trah
Tw
Tasc
Tw – 14
Tcah
Tw + 2
Tids
7
Tidh
0
Tdos
0
Tdof
Tw + 3
(Tw = 1/f)
Max. Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
– 10 –
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