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VSC8110GB

ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation

Vitesse Semiconductor 

VITESSE

VSC8110

Data Sheet

ATM/SONET/SDH 155/622 Mb/s Transceiver

Mux/Demux with Integrated Clock Generation

Features

• Operates at Either STS-3/STM-1 (155.52 Mb/s)

or STS-12/STM-4 (622.08 Mb/s) Data Rates

• Compatible with Industry ATM UNI Devices

• On Chip Clock Generation of the 155.52 Mhz or

622.08 Mhz High Speed Clock

• Reference Clock Frequencies Selectable for

19.44, 38.88, 51.84 and 77.76 Mhz

• 8 bit Parallel TTL Interface

• Integrated PLL for Clock Generation - No

External Components

• SONET/SDH Frame Recovery

• Provides Equipment and Facilities Loopback

• Low Power - 1.98 Watts Maximum

• Dual Supply Operation- +2, +5 Volts

• 100 PQFP Package

General Description

The VSC8110 is an ATM/SONET/SDH compatible transceiver integrating high speed clock generation

with 8 bit serial-to-parallel and parallel-to-serial data conversion. The high speed clock is generated using an

on-chip PLL which is selectable for 155.52 or 622.08 Mhz operation. The part can be used with 19.44, 38.88,

51.84 or 77.76 Mhz external reference clocks. The demultiplexer contains SONET/SDH frame detection and

recovery. In addition, the device provides both facility and equipment loopback modes. The part is packaged in

a 100PQFP with integrated heat spreader for optimum thermal performance and reduced cost. The VSC8110

provides an integrated solution for ATM physical layers and SONET/SDH systems applications.

Functional Description

The VSC8110 is designed to provide a SONET/SDH compliant interface between the high speed optical

networks and the lower speed User Network Interface devices such as the PM5355 S/UNI-622. The VSC8110

converts 8 bit parallel data at 77.76Mhz or 19.44Mhz to a serial bit stream at 622.08Mb/s or 155.52Mb/s respec-

tively. The transmit section provides a Facility Loopback function which loops the received high speed data and

clock directly to the transmit outputs. A clock multiplier unit is integrated into the transmit circuit to generate

the high speed clock for the serial output data stream from input reference frequencies of 19.44, 38.88, 51.84 or

77.76 Mhz. The block diagram on page 2 shows the major functional blocks associated with the VSC8110.

The receive circuit provides the serial-to-parallel conversion, converting 155Mb/s or 622Mb/s to an 8 bit

parallel output at 19.44Mhz or 77.76Mhz respectively. The receive section provides an Equipment Loopback

function which will loop the high speed transmit data and clock back through the demultiplexer to the 8 bit par-

allel outputs.

Transmit Circuit

Byte-wide data is presented to TXIN<7:0> and is clocked into the part on the rising edge of TXLSCKIN;

refer to Figure 1. The data is serialized (MSB leading) and presented at the TxOUT+/- pins. The Clock Multi-

plier Unit (CMU) generates the high speed clock required for serialization and transmission. The high speed

clock accompanying the transmitted data appears on the TxCLKOUT+/- pins. The reference clock is selectable

using the control lines BO-B2; refer to Table 13. The data rate (155Mb/s or 622Mb/s) is selected using the

STS12 control pin; refer to Table 13. The Facility Loopback mode is set by FACLOOP and is active high. A

51.84Mhz continuous clock (RX50MCK) is provided as a general board-level clock to drive other circuits such

as the UTOPIA interface on the UNI devices.

G51011-0, Rev. 1.5

® VITESSE Semiconductor Corporation

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