VSC8110GB 查看數據表（PDF） - Vitesse Semiconductor

零件编号

产品描述 (功能)

生产厂家

VSC8110GB

ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation

Vitesse Semiconductor 

VITESSE

VSC8110

Data Sheet

ATM/SONET/SDH 155/622 Mb/s Transceiver

Mux/Demux with Integrated Clock Generation

Receive Circuit

155Mb/s or 622Mb/s serial data and 155Mhz or 622Mhz clock are input to RxIN+/- and RxCLKIN+/- pins

respectively; refer to Figure 1. This data is converted to byte-wide parallel data and presented on RXOUT<7:0>

pins; refer to Figure 4. The received high speed clock is divided by 8 and presented on the RXLSCKOUT pin.

The receive circuit includes frame detection and recovery. The frame circuitry detects the SONET/SDH

frame, aligns the received serial data on byte boundaries, and initiates a frame pulse on FP coincident with the

byte aligned data. The frame recovery is initiated when OOF is held high which must occur at least 4 byte clock

cycles before the A1A2 boundary. OOF is a level-sensitive signal, and the VSC8110 will continually perform

frame detection and recovery as long as this pin is held high even if 1 or more frames has been detected. Frame

detection and recovery occurs when a series of three A1 bytes followed by three A2 bytes has been detected.

The parallel output data on RXOUT<7:0> will be byte aligned starting on the third A2 byte. When a frame is

detected, a pulse is generated on FP. The pulse FP is synchronized with the byte-aligned third A2 byte on

RXOUT<7:0>. The FP pulse is one byte clock period long. The frame detector sends an FP pulse only if OOF is

high or if a frame was detected while OOF was being pulled low.

Facility Loopback

The Facility Loopback function is controlled by the FACLOOP signal. When the FACLOOP signal is set

high, the Facility Loopback mode is activated and the high speed serial receive data (RxDATAIN) is presented

at the high speed transmit output (TxDATAOUT). In addition, the high speed receive clock input (RxCLKIN) is

selected and presented at the high speed transmit clock output (TxCLKOUT). In Facility Loopback mode the

high speed receive data (RxDATAIN) is also converted to parallel data and presented at the low speed receive

data output pins (RXOUT<7:0>). The receive clock (RxCLKIN) is also divided down and presented at the low

speed clock output (RXLSCKOUT). The Facility and Equipment Loopbacks are not designed to be enabled at

the same time.

Equipment Loopback

The Equipment Loopback function is controlled by the EQULOOP signal. When the EQULOOP signal is

set high, the Equipment Loopback mode is activated and the high speed transmit data generated from the paral-

lel to serial conversion of the low speed data (TXIN<0:7>) is selected and converted back to parallel data on the

receiver circuit side and presented at the low speed parallel outputs (RXOUT<7:0>). The internally generated

155Mhz/622Mhz clock is used to generate the low speed receive clock output (RXLSCKOUT), (Note that the

clock presented at RXLSCKOUT can be changed to present the clock applied to the EXTCLKP/N pins if the

EXTVCO control pin is set active high. In this mode EXTCLK is also presented at the TXCLKOUT and

TXLSCKOUT pins.) In Equipment Loopback mode the transmit data (TXIN<7:0>) is serialized and presented

at the high speed output (TxDATAOUT) along with the high speed transmit clock (TxCLKOUT) which is gen-

erated by the on board clock multiplier unit. The facility and Equipment Loopbacks are not designed to be

enabled at the same time.

G51011-0, Rev. 1.5

® VITESSE Semiconductor Corporation

Page 3

Share Link: