VSC8110GB 查看數據表（PDF） - Vitesse Semiconductor

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VSC8110GB

ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation

Vitesse Semiconductor 

VITESSE

VSC8110

Data Sheet

ATM/SONET/SDH 155/622 Mb/s Transceiver

Mux/Demux with Integrated Clock Generation

Table 1: Receive High Speed Data Input Timing Table (STS-12 Operation)

Parameter

TRXCLK

TRXSU

TRXH

Description

Receive clock period

Serial data setup time with respect to RxCLKIN

Serial data hold time with respect to RxCLKIN

Min

Typ

-

1.608

500

-

500

-

Table 2: Receive High Speed Data Input Timing Table (STS-3 Operation)

Parameter

TRXCLK

TRXSU

TRXH

Description

Receive clock period

Serial data setup time with respect to RxCLKIN

Serial data hold time with respect to RxCLKIN

Min

Typ

-

6.43

1.5

-

1.5

-

Figure 3: Transmit Data Input Timing Diagram

TXLSCKOUT(1)

TXLSCKIN

TPROP

TCLKIN

TINSU TINH

TXIN<7:0>

Max

-

-

-

Max

-

-

-

Units

ns

ps

ps

Units

ns

ns

ns

Table 3: Transmit Data Input Timing Table (STS-12 Operation)

Parameter

Description

Min

TCLKIN Transmit data input byte clock period

-

TINSU

Transmit data setup time with respect to TXLSCKIN

1.0

TINH

Transmit data hold time with respect to TXLSCKIN

1.0

TPROP

Maximum allowable propagation delay for connecting

TXLSCKOUT to TXLSCKIN

-

Note: Duty cycle for TXLSCKOUT is 50% +/- 5% worse case

Typ

12.86

-

-

-

Max

-

-

-

3

Units

ns

ns

ns

ns

G51011-0, Rev. 1.5

® VITESSE Semiconductor Corporation

Page 5

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