VSC8110QB1 查看數據表（PDF） - Vitesse Semiconductor

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VSC8110QB1

ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation

Vitesse Semiconductor 

VSC8110

VITESSE

ATM/SONET/SDH 155/622 Mb/s Transceiver

Mux/Demux with Integrated Clock Generation

Data Sheet

Table 4: Transmit Data Input Timing Table (STS-3 Operation)

Parameter

TCLKIN

TINSU

TINH

TPROP

Description

Transmit data input byte clock period

Transmit data setup time with respect to TXLSCKIN

Transmit data hold time with respect to TXLSCKIN

Maximum allowable propagation delay for connecting

TXLSCKOUT to TXLSCKIN

Min

Typ

Max

-

51.44

-

1.0

-

-

1.0

-

-

-

-

3

Units

ns

ns

ns

ns

Figure 4: Data and Clock Transmit Block Diagram

VSC8110

TxDATAOUT +

TxDATAOUT -

TxCLKOUT +

TxCLKOUT -

RxDATA

DQ

TxDATA

QD

CLK

TxCLK

CLK

DQ

CLK

RxCLK

8

RXOUT<7:0>

FP

RXLSCKOUT

RxCLKIN +

RxCLKIN -

RXLSCKOUT

RXOUT<7:0>

FP

Page 6

Figure 5: Receive Data Output Timing Diagram

TRXCLKIN

T RXLSCK

T RXVALID

A1

A2

A2

A2

T PW

T SKEW

® VITESSE Semiconductor Corporation

G51011-0, Rev. 1.5

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