VSC8110GB 查看數據表（PDF） - Vitesse Semiconductor

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VSC8110GB

ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation

Vitesse Semiconductor 

VITESSE

VSC8110

Data Sheet

ATM/SONET/SDH 155/622 Mb/s Transceiver

Mux/Demux with Integrated Clock Generation

Table 5: Receive Data Output Timing Table (STS-12 Operation)

Parameter

Description

Min

TRXCLKIN Receive clock period

-

TRXLSCK Receive data output byte clock period

-

TSKEW

Range in which the rising edge of FP will appear in

relation to the falling edge of RXLSCKOUT

-

TRXVALID

Time data on RXOUT<7:0> is valid before and after the

rising edge of RXLSCKOUT

4.9

TPW

Pulse width of frame detection pulse FP

-

Table 6: Receive Data Output Timing Table (STS-3 Operation)

Typ

1.608

12.86

-

-

12.86

Parameter

Description

Min

TRXCLKIN Receive clock period

-

TRXLSCKT Receive data output byte clock period

-

TSKEW

Range in which the rising edge of FP will appear in

relation to the falling edge of RXLSCKOUT

-

TRXVALID

Time data on RXOUT<7:0> is valid before and after the

rising edge of RXLSCKOUT

24

TPW

Pulse width of frame detection pulse FP

-

Typ

6.43

51.44

-

-

51.44

Figure 6: Transmit High Speed Data Timing Diagram

TTXCLK

TxCLKOUT+

TxCLKOUT-

TxDATAOUT+

TxDATAOUT-

TSKEW

Max

-

-

+/-1.5

-

-

Max

-

-

+/-1.5

-

-

Units

ns

ns

ns

ns

ns

Units

ns

ns

ns

ns

ns

G51011-0, Rev. 1.5

® VITESSE Semiconductor Corporation

Page 7

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