VSC8110QB2 查看數據表（PDF） - Vitesse Semiconductor

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VSC8110QB2

ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation

Vitesse Semiconductor 

VSC8110

VITESSE

ATM/SONET/SDH 155/622 Mb/s Transceiver

Mux/Demux with Integrated Clock Generation

Data Sheet

Table 7: Transmit High Speed Data Timing Table (STS-12 Operation)

Parameter

Description

Min

TTXCLK Transmit clock period

-

TSKEW

Skew between the falling edge of TxCLKOUT and valid

data on TxDATAOUT

-

Table 8: Transmit High Speed Data Timing Table (STS-3 Operation)

Parameter

Description

Min

TTXCLK Transmit clock period

-

TSKEW

Skew between the falling edge of TxCLKOUT and valid

data on TxDATAOUT

-

Typ

1.608

-

Max

-

+/-200

Typ

Max

6.43

-

-

+/-200

Units

ns

ps

Units

ns

ps

Data Latency

The VSC8110 contains several operating modes, each of which exercise different logic paths through the

part. Table 9 bounds the data latency through each path with an associated clock signal.

Table 9: Data Latency

Circuit

Mode

Transmit

Receive

Equipment

Loopback

Facilities

Loopback

Description

Data TXIN<7:0> to MSB at TxDATAOUT

MSB at RxDATAIN to data on RXOUT<7:0>

Byte data TXIN<7:0> to byte data on RXOUT<7:0>

MSB at RxDATAIN to MSB at TxDATAOUT

Clock

Reference

TxCLKOUT

RxCLKIN

TxCLKOUT

RxCLKIN

Range of

Clock cycles

STS-12

2-11

18-25

19-33

Range of

Clock cycles

STS-3

2-11

15-22

17-31

10

10

Page 8

® VITESSE Semiconductor Corporation

G51011-0, Rev. 1.5

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