SM5883BS 查看數據表（PDF） - Nippon Precision Circuits

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SM5883BS

Audio 3rd-order Σ∆ D/A Converter

Nippon Precision Circuits  

BLOCK DIAGRAM

LRCI

Timing

CLK

control

SM588× series

DATA

Input interface

L

R

Filter & attenuation

operation block

L

R

Noise shaper

operation block

BCKI*

DEEM**

9 Level

DEM DAC

9 Level

DEM DAC

9 Level

DEM DAC

9 Level

DEM DAC

−+

LO

VSS VDD

RO

* : Not available for 2-wire input type

** : Not available for 3-wire input type

PIN DESCRIPTION

Number

Name

I/O

Description

1

DATA

I Serial data input

BCKI1

I Bit clock input

2

DEEM 2

I Deemphasis ON/OFF control (44.1 kHz, ON when HIGH)

3

LRCI

I Sample rate (fs) clock input. Left-channel input when HIGH, and right-channel input when LOW.

4

CLK

I External clock input

5

RO

O Right-channel analog output

6

VSS

– Ground

7

VDD

– Supply

8

LO

O Left-channel analog output

1. 3-wire type

2. 2-wire type with built-in deemphasis filter

NIPPON PRECISION CIRCUITS—3

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