SP3249 查看數據表（PDF） - Signal Processing Technologies

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SP3249

Intelligent +3.0V to +5.5V RS-232 Transceivers

Signal Processing Technologies 

Charge Pump

The charge pump is a Sipex–patented design

(U.S. #5,306,954) and uses a unique approach

compared to older less–efficient designs. The

charge pump still requires four external

capacitors, but uses a four–phase voltage

shifting technique to attain symmetrical 5.5V

power supplies. The internal power supply

consists of a regulated dual charge pump that

provides output voltages 5.5V regardless of the

input voltage (VCC) over the +3.0V to +5.5V

range. This is important to maintain compliant

RS-232 levels regardless of power supply

fluctuations.

The charge pump operates in a discontinuous

mode using an internal oscillator. If the output

voltages are less than a magnitude of 5.5V, the

charge pump is enabled. If the output voltages

exceed a magnitude of 5.5V, the charge pump is

disabled. This oscillator controls the four phases

of the voltage shifting (Figure 13). A descrip-

tion of each phase follows.

Phase 1 (Figure 11)

— VSS charge storage — During this phase of

the clock cycle, the positive side of capacitors

C1 and C2 are

then switched

transferred to

tiCon2iGt–i.aNSllDiynaccnehdaCrtgh2e+edicsthoacroVgnCenCie.nctCCed1l+–

is

is

to

VCC, the voltage potential across capacitor C2 is

now 2 times VCC.

VCC

+

C5 0.1µF

VCC

C1+

+

V+

C1 0.1µF

C1-

C2+ SP3249E V-

+

C2 0.1µF

C2-

LOGIC

INPUTS

TxIN

TxOUT

LOGIC

OUTPUTS

RxOUT

RxIN

5kΩ

GND

+

C3 0.1µF

C4 0.1µF

+

1000pF

Figure 7. Loopback Test Circuit for RS-232 Driver Data

Transmission Rates

Phase 2 (Figure 12)

— VSS transfer — Phase two of the clock

connects the negative terminal of C2 to the VSS

storage capacitor and the positive terminal of C2

to GND. This transfers a negative generated

voltage to C3. This generated voltage is

regulated to a minimum voltage of -5.5V.

Simultaneous with the transfer of the voltage to

C3, the positive side of capacitor C1 is switched

to VCC and the negative side is connected to

GND.

Phase 3 (Figure 14)

Figure 8. Loopback Test Circuit Result at 120kbps

(All Drivers Fully Loaded)

Figure 9. Loopback Test Circuit result at 250kbps

(All Drivers Fully Loaded)

Rev.4/08/02

SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers

7

© Copyright 2002 Sipex Corporation

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